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An 0.8-mm(2) 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS

Dasalukunte, Deepak LU ; Rusek, Fredrik LU and Öwall, Viktor LU (2013) In IEEE Journal of Solid-State Circuits 48(7). p.1680-1688
Abstract
This paper presents an iterative decoder for faster-than-Nyquist (FTN) and orthogonal signaling multi-carrier systems. FTN signaling is a method of improving bandwidth efficiency at the expense of higher processing complexity in the transceiver. The decoder can switch between orthogonal and FTN signaling modes and exploits channel properties to improve bandwidth efficiency. The decoder is fabricated in a 65-nm CMOS process and occupies a total area of 0.8 mm(2) with decoder core taking up 0.567 mm(2). The power consumption of the chip is 9.6 mW at 1.2 V when clocked at 100 MHz, providing a peak information throughput of 1 Mbps and with an energy efficiency of 0.6 nJ per bit per iteration. To the best of our knowledge, those measurement... (More)
This paper presents an iterative decoder for faster-than-Nyquist (FTN) and orthogonal signaling multi-carrier systems. FTN signaling is a method of improving bandwidth efficiency at the expense of higher processing complexity in the transceiver. The decoder can switch between orthogonal and FTN signaling modes and exploits channel properties to improve bandwidth efficiency. The decoder is fabricated in a 65-nm CMOS process and occupies a total area of 0.8 mm(2) with decoder core taking up 0.567 mm(2). The power consumption of the chip is 9.6 mW at 1.2 V when clocked at 100 MHz, providing a peak information throughput of 1 Mbps and with an energy efficiency of 0.6 nJ per bit per iteration. To the best of our knowledge, those measurement results are from the first ever silicon implementation of a decoder for FTN signaling. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Bandwidth efficiency, faster-than-Nyquist (FTN), iterative decoder, multicarrier
in
IEEE Journal of Solid-State Circuits
volume
48
issue
7
pages
1680 - 1688
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • wos:000320938600014
  • scopus:84879962622
ISSN
0018-9200
DOI
10.1109/JSSC.2013.2253237
language
English
LU publication?
yes
id
5fb23e14-707c-40ab-be03-9eaa12eb8cce (old id 3979660)
date added to LUP
2013-09-02 16:11:33
date last changed
2019-02-20 05:15:21
@article{5fb23e14-707c-40ab-be03-9eaa12eb8cce,
  abstract     = {This paper presents an iterative decoder for faster-than-Nyquist (FTN) and orthogonal signaling multi-carrier systems. FTN signaling is a method of improving bandwidth efficiency at the expense of higher processing complexity in the transceiver. The decoder can switch between orthogonal and FTN signaling modes and exploits channel properties to improve bandwidth efficiency. The decoder is fabricated in a 65-nm CMOS process and occupies a total area of 0.8 mm(2) with decoder core taking up 0.567 mm(2). The power consumption of the chip is 9.6 mW at 1.2 V when clocked at 100 MHz, providing a peak information throughput of 1 Mbps and with an energy efficiency of 0.6 nJ per bit per iteration. To the best of our knowledge, those measurement results are from the first ever silicon implementation of a decoder for FTN signaling.},
  author       = {Dasalukunte, Deepak and Rusek, Fredrik and Öwall, Viktor},
  issn         = {0018-9200},
  keyword      = {Bandwidth efficiency,faster-than-Nyquist (FTN),iterative decoder,multicarrier},
  language     = {eng},
  number       = {7},
  pages        = {1680--1688},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Journal of Solid-State Circuits},
  title        = {An 0.8-mm(2) 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS},
  url          = {http://dx.doi.org/10.1109/JSSC.2013.2253237},
  volume       = {48},
  year         = {2013},
}