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Implementation of a Highly Scalable Architecture for Fast Inversion of Triangular Matrices

Edman, Fredrik LU and Öwall, Viktor LU (2003) IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2003 p.1137-1140
Abstract
In this paper, an F'F'GA implementation of a novel and

highly scalable hardware architecture for fast inversion of

triangular matrices is presented. An integral part of

modem signal processing and communications

applications involves manipulation of large matrices.

Therefore, scalable and flexible hardware architectures

are increasingly sought for. In this paper, the traditional

triangular shaped array architecture with n(n+1)/2

communicating processors, with n being the number of

inputs, is mapped to a linear structure with only n

processors, The linear and the triangular shaped

architectures are compared in aspect of area... (More)
In this paper, an F'F'GA implementation of a novel and

highly scalable hardware architecture for fast inversion of

triangular matrices is presented. An integral part of

modem signal processing and communications

applications involves manipulation of large matrices.

Therefore, scalable and flexible hardware architectures

are increasingly sought for. In this paper, the traditional

triangular shaped array architecture with n(n+1)/2

communicating processors, with n being the number of

inputs, is mapped to a linear structure with only n

processors, The linear and the triangular shaped

architectures are compared in aspect of area consumption,

latencies, and maximum clocking speed. This paper also

show that the linear array structure avoids drawhacks such

as non-scalability, large area, and large power

consumption. The implementation is based on a

numerically stahle recurrence algorithm, which has

excellent properties for hardware implementation. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to conference
publication status
published
subject
pages
1137 - 1140
conference name
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2003
external identifiers
  • WOS:000221510600286
  • Scopus:77956035587
language
English
LU publication?
yes
id
e40c31fd-7d7b-45a3-b2ce-1e82ed386e81 (old id 602738)
alternative location
http://ieeexplore.ieee.org/iel5/9125/28921/01301712.pdf
date added to LUP
2007-11-21 09:53:03
date last changed
2017-02-19 04:33:34
@misc{e40c31fd-7d7b-45a3-b2ce-1e82ed386e81,
  abstract     = {In this paper, an F'F'GA implementation of a novel and<br/><br>
highly scalable hardware architecture for fast inversion of<br/><br>
triangular matrices is presented. An integral part of<br/><br>
modem signal processing and communications<br/><br>
applications involves manipulation of large matrices.<br/><br>
Therefore, scalable and flexible hardware architectures<br/><br>
are increasingly sought for. In this paper, the traditional<br/><br>
triangular shaped array architecture with n(n+1)/2<br/><br>
communicating processors, with n being the number of<br/><br>
inputs, is mapped to a linear structure with only n<br/><br>
processors, The linear and the triangular shaped<br/><br>
architectures are compared in aspect of area consumption,<br/><br>
latencies, and maximum clocking speed. This paper also<br/><br>
show that the linear array structure avoids drawhacks such<br/><br>
as non-scalability, large area, and large power<br/><br>
consumption. The implementation is based on a<br/><br>
numerically stahle recurrence algorithm, which has<br/><br>
excellent properties for hardware implementation.},
  author       = {Edman, Fredrik and Öwall, Viktor},
  language     = {eng},
  pages        = {1137--1140},
  title        = {Implementation of a Highly Scalable Architecture for Fast Inversion of Triangular Matrices},
  year         = {2003},
}