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Power-driven FPGA to ASIC conversion

Fang, Wen Hai LU and Spaanenburg, Lambert LU (2007) International Symposium on Microtechnologies for the New Millennium, 2007 In Proceedings of SPIE, the International Society for Optical Engineering 6590.
Abstract
Gate arrays are often presented as a convenient means for ASIC prototyping. Obviously, they can both perform the same function and therefore be built from the same behavioral description. Design development implies a process of subsequent parameter bindings, leaving steadily less freedom for the remaining implementation choices. On the other hand, the ASIC offers more place & route freedom than the gate array. Hence it is commonly suggested that an optimal prototype will always have an acceptable ASIC realization. But this does not make the gate array an easy stepping-stone in ASIC development. Differences in platform technology induce a different structural sugaring to achieve a reasonable implementation. This cannot easily be ported,... (More)
Gate arrays are often presented as a convenient means for ASIC prototyping. Obviously, they can both perform the same function and therefore be built from the same behavioral description. Design development implies a process of subsequent parameter bindings, leaving steadily less freedom for the remaining implementation choices. On the other hand, the ASIC offers more place & route freedom than the gate array. Hence it is commonly suggested that an optimal prototype will always have an acceptable ASIC realization. But this does not make the gate array an easy stepping-stone in ASIC development. Differences in platform technology induce a different structural sugaring to achieve a reasonable implementation. This cannot easily be ported, unless the implementation is developed while keeping the restrictions for the other technology in mind. Such implies a number of scaling rules to be the foundation of the design transformation process. This paper looks into the platform commonalities of Field-Programmable Gate-arrays and standard-cell ASICs from fundamental physical principles. These basic considerations are then related to show how the area and speed restrictions in the logic synthesis can be applied to carry power efficient designs efficiently from prototype to realization. This is illustrated in the design of the SNOW-2 encryption core, where a consistent 38% power reduction is achieved. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Dynamic Power Dissipation, Application-Specific Integrated Circuit, Computational Energy, Encryption., Field-Programmable Gate-Array
in
Proceedings of SPIE, the International Society for Optical Engineering
volume
6590
publisher
SPIE
conference name
International Symposium on Microtechnologies for the New Millennium, 2007
external identifiers
  • scopus:36248958094
ISSN
0277-786X
1996-756X
ISBN
978-081946718-8
DOI
10.1117/12.722901
language
English
LU publication?
yes
id
c191feb3-33e4-4952-9940-72d1e0a41c2a (old id 603754)
date added to LUP
2007-11-22 13:32:46
date last changed
2017-11-20 15:06:01
@inproceedings{c191feb3-33e4-4952-9940-72d1e0a41c2a,
  abstract     = {Gate arrays are often presented as a convenient means for ASIC prototyping. Obviously, they can both perform the same function and therefore be built from the same behavioral description. Design development implies a process of subsequent parameter bindings, leaving steadily less freedom for the remaining implementation choices. On the other hand, the ASIC offers more place & route freedom than the gate array. Hence it is commonly suggested that an optimal prototype will always have an acceptable ASIC realization. But this does not make the gate array an easy stepping-stone in ASIC development. Differences in platform technology induce a different structural sugaring to achieve a reasonable implementation. This cannot easily be ported, unless the implementation is developed while keeping the restrictions for the other technology in mind. Such implies a number of scaling rules to be the foundation of the design transformation process. This paper looks into the platform commonalities of Field-Programmable Gate-arrays and standard-cell ASICs from fundamental physical principles. These basic considerations are then related to show how the area and speed restrictions in the logic synthesis can be applied to carry power efficient designs efficiently from prototype to realization. This is illustrated in the design of the SNOW-2 encryption core, where a consistent 38% power reduction is achieved.},
  author       = {Fang, Wen Hai and Spaanenburg, Lambert},
  booktitle    = {Proceedings of SPIE, the International Society for Optical Engineering},
  isbn         = {978-081946718-8},
  issn         = {0277-786X},
  keyword      = {Dynamic Power Dissipation,Application-Specific Integrated Circuit,Computational Energy,Encryption.,Field-Programmable Gate-Array},
  language     = {eng},
  publisher    = {SPIE},
  title        = {Power-driven FPGA to ASIC conversion},
  url          = {http://dx.doi.org/10.1117/12.722901},
  volume       = {6590},
  year         = {2007},
}