A CMOS analog FIR filter with low phase distortion
(2002) ESSCIRC 2002. Proceedings of the 28th European SolidState Circuit Conference p.747750 Abstract
 The FIR function of the proposed filter is realized by integrating weighted signal currents in a given time window on a capacitor The input signal voltage is weighted into multiple voltages according to the FIR requirement through a resistor ladder. A switching network sequentially connects the weighted voltages to a linear transconductor which converts the voltage to current and charges the capacitor. The resulting capacitor voltage becomes the filter output, periodically available between integration and reset. In such a FIR filter the hardware cost is delinked from the number of taps. The filter was implemented in a 0.35 μm CMOS process. The measured sideband attenuation reaches 60 dB while the group delay is smaller than 11 ns, with... (More)
 The FIR function of the proposed filter is realized by integrating weighted signal currents in a given time window on a capacitor The input signal voltage is weighted into multiple voltages according to the FIR requirement through a resistor ladder. A switching network sequentially connects the weighted voltages to a linear transconductor which converts the voltage to current and charges the capacitor. The resulting capacitor voltage becomes the filter output, periodically available between integration and reset. In such a FIR filter the hardware cost is delinked from the number of taps. The filter was implemented in a 0.35 μm CMOS process. The measured sideband attenuation reaches 60 dB while the group delay is smaller than 11 ns, with a power consumption of about 35 mW at 3.3 V (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/610711
 author
 Xu, Gang ^{LU} and Yuan, Jiren ^{LU}
 organization
 publishing date
 2002
 type
 Chapter in Book/Report/Conference proceeding
 publication status
 published
 subject
 keywords
 FIR function, low phase distortion, CMOS analog FIR filter, linear transconductor, finite impulse response filters, weighted voltages, 0.35 micron, 11 ns, 3.3 V, 35 mW, resistor ladder, switching network, weighted signal currents integration
 host publication
 ESSCIRC 2002. Proceedings of the 28th European SolidState Circuit Conference
 pages
 747  750
 publisher
 Univ. Bologna
 conference name
 ESSCIRC 2002. Proceedings of the 28th European SolidState Circuit Conference
 conference location
 Firenze, Italy
 conference dates
 20020924  20020926
 external identifiers

 scopus:77952194020
 ISBN
 8890084790
 language
 English
 LU publication?
 yes
 id
 aac649cb08b44366b4bae8c47f8d747a (old id 610711)
 date added to LUP
 20160404 11:10:45
 date last changed
 20200112 21:22:07
@inproceedings{aac649cb08b44366b4bae8c47f8d747a, abstract = {The FIR function of the proposed filter is realized by integrating weighted signal currents in a given time window on a capacitor The input signal voltage is weighted into multiple voltages according to the FIR requirement through a resistor ladder. A switching network sequentially connects the weighted voltages to a linear transconductor which converts the voltage to current and charges the capacitor. The resulting capacitor voltage becomes the filter output, periodically available between integration and reset. In such a FIR filter the hardware cost is delinked from the number of taps. The filter was implemented in a 0.35 μm CMOS process. The measured sideband attenuation reaches 60 dB while the group delay is smaller than 11 ns, with a power consumption of about 35 mW at 3.3 V}, author = {Xu, Gang and Yuan, Jiren}, booktitle = {ESSCIRC 2002. Proceedings of the 28th European SolidState Circuit Conference}, isbn = {8890084790}, language = {eng}, pages = {747750}, publisher = {Univ. Bologna}, title = {A CMOS analog FIR filter with low phase distortion}, year = {2002}, }