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Clock-gating of streaming applications for energy efficient implementations on FPGAs

Bezati, Endri; Casale Brunet, Simone; Mattavelli, Marco and Janneck, Jörn LU (2016) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems p.699-703
Abstract
The paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography, video analytics, network routing and packet processing and many others. The paper introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of... (More)
The paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography, video analytics, network routing and packet processing and many others. The paper introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of a high-level dataflow design flow. Experimental results of atsize applications synthesized on FPGAs platforms demonstrate power reductions achievable with no loss in data throughput. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
pages
5 pages
publisher
Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85017627352
ISSN
0278-0070
DOI
10.1109/TCAD.2016.2597215
language
English
LU publication?
yes
id
610f14fb-564f-4981-b260-515c6623988d
date added to LUP
2017-01-27 15:06:44
date last changed
2017-11-14 09:50:05
@article{610f14fb-564f-4981-b260-515c6623988d,
  abstract     = {The paper investigates the reduction of dynamic power for streaming applications yielded by asynchronous dataflow designs by using clock gating techniques. Streaming applications constitute a very broad class of computing algorithms in areas such as signal processing, digital media coding, cryptography, video analytics, network routing and packet processing and many others. The paper introduces a set of techniques that, considering the dynamic streaming behavior of algorithms, can achieve power savings by selectively switching off parts of the circuits when they are temporarily inactive. The techniques being independent from the semantic of the application can be applied to any application and can be integrated into the synthesis stage of a high-level dataflow design flow. Experimental results of atsize applications synthesized on FPGAs platforms demonstrate power reductions achievable with no loss in data throughput.},
  author       = {Bezati, Endri and Casale Brunet, Simone and Mattavelli, Marco and Janneck, Jörn},
  issn         = {0278-0070},
  language     = {eng},
  month        = {08},
  pages        = {699--703},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  title        = {Clock-gating of streaming applications for energy efficient implementations on FPGAs},
  url          = {http://dx.doi.org/10.1109/TCAD.2016.2597215},
  year         = {2016},
}