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Power optimization of a reconfigurable FIR-filter

Bruce, H; Veljanovski, R; Öwall, Viktor LU and Singh, J (2004) 2004 IEEE Workshop on Signal Processing Systems Design and Implementation In 2004 IEEE Workshop on Signal Processing Systems Design and Implementation p.321-324
Abstract
This paper describes power optimization techniques applied to a reconfigurable digital finite impulse response (FIR) filter used in a Universal Mobile Telephone Service (UMTS) mobile terminal. Various methods of optimization for implementation were combined to achieve low cost in terms of power consumption. Each optimization method is described in detail and is applied to the reconfigurable filter. The optimization methods have achieved a 78.8% reduction in complexity for the multipliers in the FIR structure. A comparison of synthesized RTL models of the original and the optimized architectures resulted in a 27% reduction in look-up tables when targeted for the Xilinx Virtex II Pro field programmable gate array (FPGA). An automated method... (More)
This paper describes power optimization techniques applied to a reconfigurable digital finite impulse response (FIR) filter used in a Universal Mobile Telephone Service (UMTS) mobile terminal. Various methods of optimization for implementation were combined to achieve low cost in terms of power consumption. Each optimization method is described in detail and is applied to the reconfigurable filter. The optimization methods have achieved a 78.8% reduction in complexity for the multipliers in the FIR structure. A comparison of synthesized RTL models of the original and the optimized architectures resulted in a 27% reduction in look-up tables when targeted for the Xilinx Virtex II Pro field programmable gate array (FPGA). An automated method for transformation of coefficient multipliers into bit-shifts is also presented (Less)
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author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
field programmable gate array, Xilinx Virtex II Pro, look-up tables, synthesized RTL models, power consumption, UMTS mobile terminal, Universal Mobile Telephone Service, digital finite impulse response filter, power optimization, reconfigurable FIR-filter, FPGA, coefficient multipliers, bit-shifts, automated method
in
2004 IEEE Workshop on Signal Processing Systems Design and Implementation
pages
321 - 324
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
2004 IEEE Workshop on Signal Processing Systems Design and Implementation
external identifiers
  • WOS:000225596900056
  • Scopus:17044407546
ISBN
0-7803-8504-7
DOI
10.1109/SIPS.2004.1363070
language
English
LU publication?
yes
id
49967011-e609-48ef-b808-1e85b4ef1316 (old id 613544)
date added to LUP
2007-11-26 17:46:04
date last changed
2017-01-01 08:07:12
@inproceedings{49967011-e609-48ef-b808-1e85b4ef1316,
  abstract     = {This paper describes power optimization techniques applied to a reconfigurable digital finite impulse response (FIR) filter used in a Universal Mobile Telephone Service (UMTS) mobile terminal. Various methods of optimization for implementation were combined to achieve low cost in terms of power consumption. Each optimization method is described in detail and is applied to the reconfigurable filter. The optimization methods have achieved a 78.8% reduction in complexity for the multipliers in the FIR structure. A comparison of synthesized RTL models of the original and the optimized architectures resulted in a 27% reduction in look-up tables when targeted for the Xilinx Virtex II Pro field programmable gate array (FPGA). An automated method for transformation of coefficient multipliers into bit-shifts is also presented},
  author       = {Bruce, H and Veljanovski, R and Öwall, Viktor and Singh, J},
  booktitle    = {2004 IEEE Workshop on Signal Processing Systems Design and Implementation},
  isbn         = {0-7803-8504-7},
  keyword      = {field programmable gate array,Xilinx Virtex II Pro,look-up tables,synthesized RTL models,power consumption,UMTS mobile terminal,Universal Mobile Telephone Service,digital finite impulse response filter,power optimization,reconfigurable FIR-filter,FPGA,coefficient multipliers,bit-shifts,automated method},
  language     = {eng},
  pages        = {321--324},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Power optimization of a reconfigurable FIR-filter},
  url          = {http://dx.doi.org/10.1109/SIPS.2004.1363070},
  year         = {2004},
}