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Area and power efficient trellis computational blocks in 0.13μm CMOS

Kamuf, Matthias LU ; Öwall, Viktor LU and Anderson, John B LU (2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 p.344-347
Abstract
Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
rate 1/2 convolutional codes, complementary property, trellis-based decoding architectures, reduced complexity, trellis computational blocks, cell area, CMOS process, branch metric unit, add-compare-select unit, 0.13 micron, power consumption, silicon implementation
host publication
IEEE International Symposium on Circuits and Systems (ISCAS)
pages
344 - 347
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2005
conference location
Kobe, Japan
conference dates
2005-05-23 - 2005-05-26
external identifiers
  • wos:000232002400087
  • scopus:67649122659
ISBN
0-7803-8834-8
DOI
10.1109/ISCAS.2005.1464595
language
English
LU publication?
yes
id
cb6a40a4-691a-4fc3-9b9d-0ae700d23374 (old id 615437)
date added to LUP
2016-04-04 11:49:09
date last changed
2022-01-29 22:31:04
@inproceedings{cb6a40a4-691a-4fc3-9b9d-0ae700d23374,
  abstract     = {{Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption}},
  author       = {{Kamuf, Matthias and Öwall, Viktor and Anderson, John B}},
  booktitle    = {{IEEE International Symposium on Circuits and Systems (ISCAS)}},
  isbn         = {{0-7803-8834-8}},
  keywords     = {{rate 1/2 convolutional codes; complementary property; trellis-based decoding architectures; reduced complexity; trellis computational blocks; cell area; CMOS process; branch metric unit; add-compare-select unit; 0.13 micron; power consumption; silicon implementation}},
  language     = {{eng}},
  pages        = {{344--347}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Area and power efficient trellis computational blocks in 0.13μm CMOS}},
  url          = {{https://lup.lub.lu.se/search/files/5862409/634007.pdf}},
  doi          = {{10.1109/ISCAS.2005.1464595}},
  year         = {{2005}},
}