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Area and power efficient trellis computational blocks in 0.13μm CMOS

Kamuf, Matthias LU ; Öwall, Viktor LU and Anderson, John B LU (2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 In IEEE International Symposium on Circuits and Systems (ISCAS) p.344-347
Abstract
Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
rate 1/2 convolutional codes, complementary property, trellis-based decoding architectures, reduced complexity, trellis computational blocks, cell area, CMOS process, branch metric unit, add-compare-select unit, 0.13 micron, power consumption, silicon implementation
in
IEEE International Symposium on Circuits and Systems (ISCAS)
pages
344 - 347
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2005
external identifiers
  • wos:000232002400087
  • scopus:67649122659
ISBN
0-7803-8834-8
DOI
10.1109/ISCAS.2005.1464595
language
English
LU publication?
yes
id
cb6a40a4-691a-4fc3-9b9d-0ae700d23374 (old id 615437)
date added to LUP
2007-11-25 12:54:28
date last changed
2017-01-01 08:05:28
@inproceedings{cb6a40a4-691a-4fc3-9b9d-0ae700d23374,
  abstract     = {Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption},
  author       = {Kamuf, Matthias and Öwall, Viktor and Anderson, John B},
  booktitle    = {IEEE International Symposium on Circuits and Systems (ISCAS)},
  isbn         = {0-7803-8834-8},
  keyword      = {rate 1/2 convolutional codes,complementary property,trellis-based decoding architectures,reduced complexity,trellis computational blocks,cell area,CMOS process,branch metric unit,add-compare-select unit,0.13 micron,power consumption,silicon implementation},
  language     = {eng},
  pages        = {344--347},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Area and power efficient trellis computational blocks in 0.13μm CMOS},
  url          = {http://dx.doi.org/10.1109/ISCAS.2005.1464595},
  year         = {2005},
}