A scalable pipelined complex valued matrix inversion architecture
(2005) IEEE International Symposium on Circuits and Systems (ISCAS), 2005 p.4489-4492- Abstract
- This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>-1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic... (More)
- This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>-1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/616135
- author
- Edman, F and Öwall, Viktor LU
- organization
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- squared Givens rotations algorithm, recurrence algorithm, triangular matrix, linear array architecture, smart antenna systems, fixed-point representation arithmetic operations, 12 bit, QR-factorization, complex valued matrix inversion, FPGA implementation, scalable pipelined architecture
- host publication
- IEEE International Symposium on Circuits and Systems (ISCAS)
- pages
- 4489 - 4492
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Symposium on Circuits and Systems (ISCAS), 2005
- conference location
- Kobe, Japan
- conference dates
- 2005-05-23 - 2005-05-26
- external identifiers
-
- wos:000232002404079
- scopus:49149097777
- ISBN
- 0-7803-8834-8
- DOI
- 10.1109/ISCAS.2005.1465629
- language
- English
- LU publication?
- yes
- id
- 97b86b64-c937-411b-a3ab-1858bacc0535 (old id 616135)
- date added to LUP
- 2016-04-04 10:26:30
- date last changed
- 2022-04-23 22:59:07
@inproceedings{97b86b64-c937-411b-a3ab-1858bacc0535, abstract = {{This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R<sup>-1</sup> with Q. We show that traditional triangular array architectures employing O(n<sup>2</sup>) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system}}, author = {{Edman, F and Öwall, Viktor}}, booktitle = {{IEEE International Symposium on Circuits and Systems (ISCAS)}}, isbn = {{0-7803-8834-8}}, keywords = {{squared Givens rotations algorithm; recurrence algorithm; triangular matrix; linear array architecture; smart antenna systems; fixed-point representation arithmetic operations; 12 bit; QR-factorization; complex valued matrix inversion; FPGA implementation; scalable pipelined architecture}}, language = {{eng}}, pages = {{4489--4492}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{A scalable pipelined complex valued matrix inversion architecture}}, url = {{http://dx.doi.org/10.1109/ISCAS.2005.1465629}}, doi = {{10.1109/ISCAS.2005.1465629}}, year = {{2005}}, }