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Scalable low-latency systolic arrays using toroidal and bi-directional dataflows

Svensson, Linus ; Gustafsson, Oscar and Rodrigues, Joachim LU (2025) 2025 IEEE Workshop on Signal Processing Systems, SiPS 2025
Abstract

Systolic arrays (SAs) for matrix multiplication are commonly used in machine learning (ML), wireless communication, and signal processing. Inherently offering high throughput with good data reuse, they are well-positioned for both low-power edge devices and accelerator applications in high-performance computing. Current realizations suffer from startup latency, defined as the time required to fully utilize all processing elements (PEs). In this work, this issue is addressed by introducing bidirectional systolic arrays with connected edges that form toroidal dataflows. The proposed systolic arrays significantly reduce computational and readout latency from 4 n-2 to 2.5 n-1 clock cycles for an n × n matrix multiplication, while... (More)

Systolic arrays (SAs) for matrix multiplication are commonly used in machine learning (ML), wireless communication, and signal processing. Inherently offering high throughput with good data reuse, they are well-positioned for both low-power edge devices and accelerator applications in high-performance computing. Current realizations suffer from startup latency, defined as the time required to fully utilize all processing elements (PEs). In this work, this issue is addressed by introducing bidirectional systolic arrays with connected edges that form toroidal dataflows. The proposed systolic arrays significantly reduce computational and readout latency from 4 n-2 to 2.5 n-1 clock cycles for an n × n matrix multiplication, while simultaneously reducing energy per operation by up to 43% compared to conventional SAs. Moreover, a variety of differently shaped SAs are synthesized in a 22 nm CMOS technology, and it is shown that the toroidal designs offer a 5%-12% lower silicon area cost.

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Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
NPU, Systolic arrays, Toroidal dataflow, TPU
host publication
2025 IEEE Workshop on Signal Processing Systems (SiPS). 1-4 Nov. 2025
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
2025 IEEE Workshop on Signal Processing Systems, SiPS 2025
conference location
Hong Kong, Hong Kong
conference dates
2025-11-01 - 2025-11-04
external identifiers
  • scopus:105031673264
ISBN
979-8-3315-9831-0
DOI
10.1109/SiPS66314.2025.11261266
language
English
LU publication?
yes
id
62f9d060-d53f-4b1b-b89b-ccca283124ea
date added to LUP
2026-08-21 06:23:19
date last changed
2026-09-16 15:04:59
@inproceedings{62f9d060-d53f-4b1b-b89b-ccca283124ea,
  abstract     = {{<p>Systolic arrays (SAs) for matrix multiplication are commonly used in machine learning (ML), wireless communication, and signal processing. Inherently offering high throughput with good data reuse, they are well-positioned for both low-power edge devices and accelerator applications in high-performance computing. Current realizations suffer from startup latency, defined as the time required to fully utilize all processing elements (PEs). In this work, this issue is addressed by introducing bidirectional systolic arrays with connected edges that form toroidal dataflows. The proposed systolic arrays significantly reduce computational and readout latency from 4 n-2 to 2.5 n-1 clock cycles for an n × n matrix multiplication, while simultaneously reducing energy per operation by up to 43% compared to conventional SAs. Moreover, a variety of differently shaped SAs are synthesized in a 22 nm CMOS technology, and it is shown that the toroidal designs offer a 5%-12% lower silicon area cost.</p>}},
  author       = {{Svensson, Linus and Gustafsson, Oscar and Rodrigues, Joachim}},
  booktitle    = {{2025 IEEE Workshop on Signal Processing Systems (SiPS). 1-4 Nov. 2025}},
  isbn         = {{979-8-3315-9831-0}},
  keywords     = {{NPU; Systolic arrays; Toroidal dataflow; TPU}},
  language     = {{eng}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Scalable low-latency systolic arrays using toroidal and bi-directional dataflows}},
  url          = {{http://dx.doi.org/10.1109/SiPS66314.2025.11261266}},
  doi          = {{10.1109/SiPS66314.2025.11261266}},
  year         = {{2025}},
}