Estimating Stream Application Performance in Early-Stage System Design
Callanan, Gareth LU and Gruian, Flavius LU
(2022)
2022 56th Asilomar Conference on Signals, Systems, and Computers
p.816-823
- Abstract
- When designing a hardware architecture, a designer needs to be confident that their design will meet performance requirements before moving on to the next stage in the design process. The mapping between application and architecture can have a large impact on the system performance. In this work we target early-stage system design of hardware architectures required to run a streaming application. Our aim is to improve a designer's insight and visibility into the system. We present an approach where a designer chooses a representative application described as a dataflow algorithm as well as a mapping between the application and architecture. The designer then simulates the execution of this application on a model of the system architecture.... (More)
- When designing a hardware architecture, a designer needs to be confident that their design will meet performance requirements before moving on to the next stage in the design process. The mapping between application and architecture can have a large impact on the system performance. In this work we target early-stage system design of hardware architectures required to run a streaming application. Our aim is to improve a designer's insight and visibility into the system. We present an approach where a designer chooses a representative application described as a dataflow algorithm as well as a mapping between the application and architecture. The designer then simulates the execution of this application on a model of the system architecture. Using the performance figures from the simulation, the designer can decide to either modify their mapping, adjust their architecture or move to the next stage in the design process. This paper focuses on the simulation part of our approach. We first unroll the execution of the application into a trace. We have created a simulation engine that takes this trace and the mapping, simulates its performance on a lightweight SystemC model of the hardware architecture and produces metrics as an output. Validation on a real platform shows that our simulated results are accurate to within 10%. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/657bcd32-3084-4f2a-8e3e-388f631bb96f
- author
- Callanan, Gareth
LU
and Gruian, Flavius
LU
- organization
- publishing date
- 2022
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2022 56th Asilomar Conference on Signals, Systems, and Computers
- pages
- 816 - 823
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 2022 56th Asilomar Conference on Signals, Systems, and Computers
- conference location
- Pacific Grove, United States
- conference dates
- 2022-10-31 - 2022-11-02
- external identifiers
-
- scopus:85150200706
- ISBN
- 978-1-6654-5907-5
- 978-1-6654-5906-8
- DOI
- 10.1109/IEEECONF56349.2022.10051859
- project
- Investigation on Describing, Compiling and Analysing Scalable Dataflow Actor Networks in Streaming Applications
- language
- English
- LU publication?
- yes
- id
- 657bcd32-3084-4f2a-8e3e-388f631bb96f
- date added to LUP
- 2023-03-10 08:59:59
- date last changed
- 2024-06-25 05:13:34
@inproceedings{657bcd32-3084-4f2a-8e3e-388f631bb96f,
abstract = {{When designing a hardware architecture, a designer needs to be confident that their design will meet performance requirements before moving on to the next stage in the design process. The mapping between application and architecture can have a large impact on the system performance. In this work we target early-stage system design of hardware architectures required to run a streaming application. Our aim is to improve a designer's insight and visibility into the system. We present an approach where a designer chooses a representative application described as a dataflow algorithm as well as a mapping between the application and architecture. The designer then simulates the execution of this application on a model of the system architecture. Using the performance figures from the simulation, the designer can decide to either modify their mapping, adjust their architecture or move to the next stage in the design process. This paper focuses on the simulation part of our approach. We first unroll the execution of the application into a trace. We have created a simulation engine that takes this trace and the mapping, simulates its performance on a lightweight SystemC model of the hardware architecture and produces metrics as an output. Validation on a real platform shows that our simulated results are accurate to within 10%.}},
author = {{Callanan, Gareth and Gruian, Flavius}},
booktitle = {{2022 56th Asilomar Conference on Signals, Systems, and Computers}},
isbn = {{978-1-6654-5907-5}},
language = {{eng}},
pages = {{816--823}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Estimating Stream Application Performance in Early-Stage System Design}},
url = {{http://dx.doi.org/10.1109/IEEECONF56349.2022.10051859}},
doi = {{10.1109/IEEECONF56349.2022.10051859}},
year = {{2022}},
}