Low power analog channel decoder in sub-threshold 65nm CMOS
(2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)- Abstract
- This paper presents the architecture and the corresponding
simulation results for a very low power half-rate
extended Hamming (8,4) decoder implemented in analog integrated
circuitry. TI’s 65nm low power CMOS design library
was used to simulate the complete decoder including an input
interface, an analog decoding core and an output interface. The
simulated bit error rate (BER) performance of the decoder is
presented and compared to the ideal performance expected from
the Hamming code. Transistor-level simulation results suggest
that a high throughput Hamming decoder up to 1 Mbits can be
implemented in analog circuits with a core power... (More) - This paper presents the architecture and the corresponding
simulation results for a very low power half-rate
extended Hamming (8,4) decoder implemented in analog integrated
circuitry. TI’s 65nm low power CMOS design library
was used to simulate the complete decoder including an input
interface, an analog decoding core and an output interface. The
simulated bit error rate (BER) performance of the decoder is
presented and compared to the ideal performance expected from
the Hamming code. Transistor-level simulation results suggest
that a high throughput Hamming decoder up to 1 Mbits can be
implemented in analog circuits with a core power consumption
as low as 6 μW. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1689598
- author
- Meraji, Reza LU ; Anderson, John B LU and Öwall, Viktor LU
- organization
-
- Department of Electrical and Information Technology
- Telecommunication Theory-lup-obsolete (research group)
- Digital ASIC-lup-obsolete (research group)
- Analog RF-lup-obsolete (research group)
- Elektronikkonstruktion-lup-obsolete (research group)
- ELLIIT: the Linköping-Lund initiative on IT and mobile communication
- publishing date
- 2010
- type
- Contribution to conference
- publication status
- published
- subject
- keywords
- sub-threshold CMOS, integrated circuits, low power circuits, Decoders
- pages
- 4 pages
- conference name
- Swedish System-on-Chip Conference 2010 (SSoCC'10)
- conference location
- Kolmården, Sweden
- conference dates
- 2010-05-03 - 2010-05-04
- language
- English
- LU publication?
- yes
- id
- 67ad6381-dc7b-4797-a61a-ebc89889b342 (old id 1689598)
- date added to LUP
- 2016-04-04 11:01:35
- date last changed
- 2019-12-09 13:57:49
@misc{67ad6381-dc7b-4797-a61a-ebc89889b342,
abstract = {{This paper presents the architecture and the corresponding<br/><br>
simulation results for a very low power half-rate<br/><br>
extended Hamming (8,4) decoder implemented in analog integrated<br/><br>
circuitry. TI’s 65nm low power CMOS design library<br/><br>
was used to simulate the complete decoder including an input<br/><br>
interface, an analog decoding core and an output interface. The<br/><br>
simulated bit error rate (BER) performance of the decoder is<br/><br>
presented and compared to the ideal performance expected from<br/><br>
the Hamming code. Transistor-level simulation results suggest<br/><br>
that a high throughput Hamming decoder up to 1 Mbits can be<br/><br>
implemented in analog circuits with a core power consumption<br/><br>
as low as 6 μW.}},
author = {{Meraji, Reza and Anderson, John B and Öwall, Viktor}},
keywords = {{sub-threshold CMOS; integrated circuits; low power circuits; Decoders}},
language = {{eng}},
title = {{Low power analog channel decoder in sub-threshold 65nm CMOS}},
year = {{2010}},
}