Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS
(2013) IEEE European Solid State Circuits Conference, ESSCIRC 2013 p.192-200- Abstract
- Two standard-cell based memories (SCMs) for op- eration in the subthreshold (sub-VT) region are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual- VT approach to balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implemen- tation; and 2) a purely MUX-based implementation with the 1st stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65 nm CMOS technology show that read access speed increases by 4X and 8X compared to a... (More)
- Two standard-cell based memories (SCMs) for op- eration in the subthreshold (sub-VT) region are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual- VT approach to balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implemen- tation; and 2) a purely MUX-based implementation with the 1st stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65 nm CMOS technology show that read access speed increases by 4X and 8X compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7X and 2X to 39 and 29 fJ, respectively. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/3812696
- author
- Andersson, Oskar LU ; Mohammadi, Babak LU ; Meinerzhagen, Pascal ; Burg, Andreas and Rodrigues, Joachim LU
- organization
- publishing date
- 2013
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- Proceedings of the ESSCIRC (ESSCIRC), 2013
- pages
- 192 - 200
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE European Solid State Circuits Conference, ESSCIRC 2013
- conference location
- Bucharest, Romania
- conference dates
- 2013-09-16 - 2013-09-20
- external identifiers
-
- scopus:84891114305
- ISSN
- 1930-8833
- ISBN
- 978-1-4799-0643-7
- DOI
- 10.1109/ESSCIRC.2013.6649106
- language
- English
- LU publication?
- yes
- id
- 6ee72055-2228-4ff9-a462-879ebf037ab7 (old id 3812696)
- date added to LUP
- 2016-04-01 13:02:39
- date last changed
- 2022-01-27 17:00:51
@inproceedings{6ee72055-2228-4ff9-a462-879ebf037ab7, abstract = {{Two standard-cell based memories (SCMs) for op- eration in the subthreshold (sub-VT) region are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual- VT approach to balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implemen- tation; and 2) a purely MUX-based implementation with the 1st stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65 nm CMOS technology show that read access speed increases by 4X and 8X compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7X and 2X to 39 and 29 fJ, respectively.}}, author = {{Andersson, Oskar and Mohammadi, Babak and Meinerzhagen, Pascal and Burg, Andreas and Rodrigues, Joachim}}, booktitle = {{Proceedings of the ESSCIRC (ESSCIRC), 2013}}, isbn = {{978-1-4799-0643-7}}, issn = {{1930-8833}}, language = {{eng}}, pages = {{192--200}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, title = {{Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS}}, url = {{http://dx.doi.org/10.1109/ESSCIRC.2013.6649106}}, doi = {{10.1109/ESSCIRC.2013.6649106}}, year = {{2013}}, }