Novel MIMO Detection Algorithm for High-order Constellations in the Complex Domain
(2012) In IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21(5). p.834-847- Abstract
- A novel detection algorithm with an efficient VLSI architecture featuring efficient operation over infinite complex lattices is proposed. The proposed design results in the highest throughput, the lowest latency, and the lowest energy compared to the complex-domain VLSI implementations to date. The main innovations are a novel complex-domain means of expanding/visiting the intermediate nodes of the search tree on demand, rather than exhaustively, as well as a new distributed sorting scheme to keep track of the best candidates at each search phase. Its support of unbounded infinite lattice decoding distinguishes the present method from previous K-Best strategies and also allows its complexity to scale sublinearly with the modulation order.... (More)
- A novel detection algorithm with an efficient VLSI architecture featuring efficient operation over infinite complex lattices is proposed. The proposed design results in the highest throughput, the lowest latency, and the lowest energy compared to the complex-domain VLSI implementations to date. The main innovations are a novel complex-domain means of expanding/visiting the intermediate nodes of the search tree on demand, rather than exhaustively, as well as a new distributed sorting scheme to keep track of the best candidates at each search phase. Its support of unbounded infinite lattice decoding distinguishes the present method from previous K-Best strategies and also allows its complexity to scale sublinearly with the modulation order. Since the expansion and sorting cores are data-driven, the architecture is well suited for a pipelined parallel VLSI implementation. The proposed algorithm is used to fabricate a 4×4, 64-QAM complex multiple-input-multiple-output detector in a 0.13-μm CMOS technology, achieving a clock rate of 417 MHz with the core area of 340 kgates. The chip test results prove that the fabricated design can sustain a throughput of 1 Gb/s with energy efficiency of 110 pJ/bit, the best numbers reported to date. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/74977247-d9e1-409c-80bf-8e2b1837898b
- author
- Mahdavi, Mojtaba LU and Shabany, Mahdi
- organization
- publishing date
- 2012-05-15
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- MIMO detection, VLSI architecture, ASIC implementation, high throughput, LTE
- in
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- volume
- 21
- issue
- 5
- pages
- 834 - 847
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:84876796119
- ISSN
- 1063-8210
- DOI
- 10.1109/TVLSI.2012.2196296
- language
- English
- LU publication?
- no
- id
- 74977247-d9e1-409c-80bf-8e2b1837898b
- date added to LUP
- 2016-12-24 17:00:32
- date last changed
- 2022-02-21 23:09:57
@article{74977247-d9e1-409c-80bf-8e2b1837898b, abstract = {{A novel detection algorithm with an efficient VLSI architecture featuring efficient operation over infinite complex lattices is proposed. The proposed design results in the highest throughput, the lowest latency, and the lowest energy compared to the complex-domain VLSI implementations to date. The main innovations are a novel complex-domain means of expanding/visiting the intermediate nodes of the search tree on demand, rather than exhaustively, as well as a new distributed sorting scheme to keep track of the best candidates at each search phase. Its support of unbounded infinite lattice decoding distinguishes the present method from previous K-Best strategies and also allows its complexity to scale sublinearly with the modulation order. Since the expansion and sorting cores are data-driven, the architecture is well suited for a pipelined parallel VLSI implementation. The proposed algorithm is used to fabricate a 4×4, 64-QAM complex multiple-input-multiple-output detector in a 0.13-μm CMOS technology, achieving a clock rate of 417 MHz with the core area of 340 kgates. The chip test results prove that the fabricated design can sustain a throughput of 1 Gb/s with energy efficiency of 110 pJ/bit, the best numbers reported to date.}}, author = {{Mahdavi, Mojtaba and Shabany, Mahdi}}, issn = {{1063-8210}}, keywords = {{MIMO detection; VLSI architecture; ASIC implementation; high throughput; LTE}}, language = {{eng}}, month = {{05}}, number = {{5}}, pages = {{834--847}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}}, title = {{Novel MIMO Detection Algorithm for High-order Constellations in the Complex Domain}}, url = {{http://dx.doi.org/10.1109/TVLSI.2012.2196296}}, doi = {{10.1109/TVLSI.2012.2196296}}, volume = {{21}}, year = {{2012}}, }