Design of highly-parallel, 2.2Gbps throughput signal detector for MIMO systems
Liu, Liang LU
; Ma, Xiaojing
; Ye, Fan
and Ren, Junyan
(2008)
IEEE International Conference on Communications ICC 2008
p.742-745
- Abstract
- This paper presents a field-programmable gate array (FPGA) implementation of a new multiple-input multiple-output (MIMO) signal detection algorithm applicable to ultra-high throughput MIMO communication systems. The algorithm simplifies the computation significantly compared to traditional K-Best algorithm, and with negligible bit error ratio (BER) degradation. A highly-parallel structure is implemented on the Xilinx Virtex-4 (XC4VLX200) platform, which achieves 2.2 Gbps detection throughput and is about four times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 6.79 ns. Together with... (More)
- This paper presents a field-programmable gate array (FPGA) implementation of a new multiple-input multiple-output (MIMO) signal detection algorithm applicable to ultra-high throughput MIMO communication systems. The algorithm simplifies the computation significantly compared to traditional K-Best algorithm, and with negligible bit error ratio (BER) degradation. A highly-parallel structure is implemented on the Xilinx Virtex-4 (XC4VLX200) platform, which achieves 2.2 Gbps detection throughput and is about four times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 6.79 ns. Together with candidate-sharing-architecture to further save the hardware cost, a high speed, compact signal detector for MIMO systems is demonstrated. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/1686565
- author
- Liu, Liang
LU
; Ma, Xiaojing
; Ye, Fan
and Ren, Junyan
- publishing date
- 2008
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- [Host publication title missing]
- pages
- 742 - 745
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- IEEE International Conference on Communications ICC 2008
- conference location
- Beijing, China
- conference dates
- 2008-05-19 - 2008-05-23
- external identifiers
-
- scopus:51249088573
- ISBN
- 978-1-4244-2075-9
- DOI
- 10.1109/ICC.2008.145
- language
- English
- LU publication?
- no
- id
- 78a67edc-7565-48a5-8c86-5e19b2cf0efa (old id 1686565)
- date added to LUP
- 2016-04-04 11:11:49
- date last changed
- 2024-01-12 23:38:43
@inproceedings{78a67edc-7565-48a5-8c86-5e19b2cf0efa,
abstract = {{This paper presents a field-programmable gate array (FPGA) implementation of a new multiple-input multiple-output (MIMO) signal detection algorithm applicable to ultra-high throughput MIMO communication systems. The algorithm simplifies the computation significantly compared to traditional K-Best algorithm, and with negligible bit error ratio (BER) degradation. A highly-parallel structure is implemented on the Xilinx Virtex-4 (XC4VLX200) platform, which achieves 2.2 Gbps detection throughput and is about four times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 6.79 ns. Together with candidate-sharing-architecture to further save the hardware cost, a high speed, compact signal detector for MIMO systems is demonstrated.}},
author = {{Liu, Liang and Ma, Xiaojing and Ye, Fan and Ren, Junyan}},
booktitle = {{[Host publication title missing]}},
isbn = {{978-1-4244-2075-9}},
language = {{eng}},
pages = {{742--745}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{Design of highly-parallel, 2.2Gbps throughput signal detector for MIMO systems}},
url = {{http://dx.doi.org/10.1109/ICC.2008.145}},
doi = {{10.1109/ICC.2008.145}},
year = {{2008}},
}