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A hardware efficiency analysis for simplified trellis decoding blocks

Kamuf, Matthias LU ; Öwall, Viktor LU and Anderson, John B LU (2005) IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS) 2005. p.128-132
Abstract
Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Trellis decoding blocks, Computational operations, Hardware efficiency
host publication
[Host publication title missing]
volume
2005
pages
128 - 132
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE Workshop on Signal Processing Systems - Design and Implementation (SiPS)
conference location
Athens, Greece
conference dates
2005-11-02 - 2005-11-04
external identifiers
  • wos:000236758900023
  • scopus:33846986763
ISSN
1520-6130
ISBN
0-7803-9333-3
DOI
10.1109/SIPS.2005.1579851
language
English
LU publication?
yes
id
85a9bb57-e15b-40f2-ba8c-fb669b881a42 (old id 615620)
date added to LUP
2016-04-01 16:46:17
date last changed
2025-04-04 15:13:42
@inproceedings{85a9bb57-e15b-40f2-ba8c-fb669b881a42,
  abstract     = {{Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.}},
  author       = {{Kamuf, Matthias and Öwall, Viktor and Anderson, John B}},
  booktitle    = {{[Host publication title missing]}},
  isbn         = {{0-7803-9333-3}},
  issn         = {{1520-6130}},
  keywords     = {{Trellis decoding blocks; Computational operations; Hardware efficiency}},
  language     = {{eng}},
  pages        = {{128--132}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A hardware efficiency analysis for simplified trellis decoding blocks}},
  url          = {{http://dx.doi.org/10.1109/SIPS.2005.1579851}},
  doi          = {{10.1109/SIPS.2005.1579851}},
  volume       = {{2005}},
  year         = {{2005}},
}