A hardware efficiency analysis for simplified trellis decoding blocks
(2005) 2005. p.128-132- Abstract
- Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.
Please use this url to cite or link to this publication:
http://lup.lub.lu.se/record/615620
- author
- Kamuf, Matthias LU ; Öwall, Viktor LU and Anderson, John B LU
- organization
- publishing date
- 2005
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- Trellis decoding blocks, Computational operations, Hardware efficiency
- host publication
- [Host publication title missing]
- volume
- 2005
- pages
- 128 - 132
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- wos:000236758900023
- scopus:33846986763
- ISSN
- 1520-6130
- ISBN
- 0-7803-9333-3
- DOI
- 10.1109/SIPS.2005.1579851
- language
- English
- LU publication?
- yes
- id
- 85a9bb57-e15b-40f2-ba8c-fb669b881a42 (old id 615620)
- date added to LUP
- 2016-04-01 16:46:17
- date last changed
- 2019-02-20 08:12:32
@inproceedings{85a9bb57-e15b-40f2-ba8c-fb669b881a42, abstract = {Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.}, author = {Kamuf, Matthias and Öwall, Viktor and Anderson, John B}, booktitle = {[Host publication title missing]}, isbn = {0-7803-9333-3}, issn = {1520-6130}, language = {eng}, pages = {128--132}, publisher = {IEEE - Institute of Electrical and Electronics Engineers Inc.}, title = {A hardware efficiency analysis for simplified trellis decoding blocks}, url = {http://dx.doi.org/10.1109/SIPS.2005.1579851}, doi = {10.1109/SIPS.2005.1579851}, volume = {2005}, year = {2005}, }