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A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI

Nouripayam, Masoud LU ; Rodrigues, Joachim LU ; Luo, Xiao ; Johansson, Tom and Mohammadi, Babak (2021) 47th IEEE European Solid State Circuits Conference, ESSCIRC 2021 In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings p.459-462
Abstract

A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29 V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80 MHz access rate, at a VDD of 0.54 V.

Please use this url to cite or link to this publication:
author
; ; ; and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
6T bitcell, boost-assist, dual-port, low-power, low-voltage, single-ended read, SRAM
host publication
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
series title
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings
pages
4 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
47th IEEE European Solid State Circuits Conference, ESSCIRC 2021
conference location
Virtual, Online, France
conference dates
2021-09-06 - 2021-09-09
external identifiers
  • scopus:85118430844
ISBN
978-1-6654-3751-6
DOI
10.1109/ESSCIRC53450.2021.9567785
language
English
LU publication?
yes
additional info
Publisher Copyright: © 2021 IEEE.
id
8b32eb8d-6b4e-481c-ad3b-429a2962e870
date added to LUP
2021-12-02 09:26:07
date last changed
2022-05-05 06:22:48
@inproceedings{8b32eb8d-6b4e-481c-ad3b-429a2962e870,
  abstract     = {{<p>A 32 Kb dual-port low-voltage SRAM in 28 nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual-port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29 V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80 MHz access rate, at a VDD of 0.54 V. </p>}},
  author       = {{Nouripayam, Masoud and Rodrigues, Joachim and Luo, Xiao and Johansson, Tom and Mohammadi, Babak}},
  booktitle    = {{ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings}},
  isbn         = {{978-1-6654-3751-6}},
  keywords     = {{6T bitcell; boost-assist; dual-port; low-power; low-voltage; single-ended read; SRAM}},
  language     = {{eng}},
  month        = {{09}},
  pages        = {{459--462}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference, Proceedings}},
  title        = {{A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI}},
  url          = {{http://dx.doi.org/10.1109/ESSCIRC53450.2021.9567785}},
  doi          = {{10.1109/ESSCIRC53450.2021.9567785}},
  year         = {{2021}},
}