Low-Complexity Binary Morphology Architectures with Flat Rectangular Structure Elements
(2008) In IEEE Transactions on Circuits and Systems Part 1: Regular Papers 55(8). p.2216-2225- Abstract
- This article describes and evaluates algorithms and their hardware architectures for binary morphological erosion and dilation. In particular, a fast stall-free low-complexity architecture is proposed that takes advantage of the morphological duality principle and structuring element (SE) decomposition. The design is intended to be used as a hardware accelerator in real-time embedded processing applications. Hence, the aim is to minimize the number of operations, memory requirement, and memory accesses per pixel. The main advantage of the proposed architecture is that for the common class of flat and rectangular SEs, complexity and number of memory accesses per pixel is low and independent of both image and SE size. The proposed design is... (More)
- This article describes and evaluates algorithms and their hardware architectures for binary morphological erosion and dilation. In particular, a fast stall-free low-complexity architecture is proposed that takes advantage of the morphological duality principle and structuring element (SE) decomposition. The design is intended to be used as a hardware accelerator in real-time embedded processing applications. Hence, the aim is to minimize the number of operations, memory requirement, and memory accesses per pixel. The main advantage of the proposed architecture is that for the common class of flat and rectangular SEs, complexity and number of memory accesses per pixel is low and independent of both image and SE size. The proposed design is compared to the more common delay-line architecture in terms of complexity, memory requirements and execution time, both for an actual implementation and as a function of image resolution and SE size. The architecture is implemented for the UMC 0.13- $mu{hbox {m}}$ CMOS process using a resolution of 640 $times$ 480. A maximum SE of 63 $times$ 63 is supported at an estimated clock frequency of 333 MHz. (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/960837
- author
- Hedberg, Hugo LU ; Kristensen, Fredrik and Öwall, Viktor LU
- organization
- publishing date
- 2008
- type
- Contribution to journal
- publication status
- published
- subject
- in
- IEEE Transactions on Circuits and Systems Part 1: Regular Papers
- volume
- 55
- issue
- 8
- pages
- 2216 - 2225
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- wos:000259499400006
- scopus:54749084321
- ISSN
- 1549-8328
- DOI
- 10.1109/TCSI.2008.918140
- language
- English
- LU publication?
- yes
- id
- 88558f88-aa71-4e07-8d4a-d841f44ad261 (old id 960837)
- alternative location
- http://ieeexplore.ieee.org/iel5/8919/4358591/04447930.pdf
- date added to LUP
- 2016-04-01 11:48:53
- date last changed
- 2022-01-26 18:41:13
@article{88558f88-aa71-4e07-8d4a-d841f44ad261,
abstract = {{This article describes and evaluates algorithms and their hardware architectures for binary morphological erosion and dilation. In particular, a fast stall-free low-complexity architecture is proposed that takes advantage of the morphological duality principle and structuring element (SE) decomposition. The design is intended to be used as a hardware accelerator in real-time embedded processing applications. Hence, the aim is to minimize the number of operations, memory requirement, and memory accesses per pixel. The main advantage of the proposed architecture is that for the common class of flat and rectangular SEs, complexity and number of memory accesses per pixel is low and independent of both image and SE size. The proposed design is compared to the more common delay-line architecture in terms of complexity, memory requirements and execution time, both for an actual implementation and as a function of image resolution and SE size. The architecture is implemented for the UMC 0.13- $mu{hbox {m}}$ CMOS process using a resolution of 640 $times$ 480. A maximum SE of 63 $times$ 63 is supported at an estimated clock frequency of 333 MHz.}},
author = {{Hedberg, Hugo and Kristensen, Fredrik and Öwall, Viktor}},
issn = {{1549-8328}},
language = {{eng}},
number = {{8}},
pages = {{2216--2225}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
series = {{IEEE Transactions on Circuits and Systems Part 1: Regular Papers}},
title = {{Low-Complexity Binary Morphology Architectures with Flat Rectangular Structure Elements}},
url = {{https://lup.lub.lu.se/search/files/2653693/1580339.pdf}},
doi = {{10.1109/TCSI.2008.918140}},
volume = {{55}},
year = {{2008}},
}