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Architecture Design of a Memory Subsystem for Massive MIMO Baseband Processing

Liu, Yangxurui LU ; Liu, Liang LU and Öwall, Viktor LU (2017) In IEEE Transactions on Very Large Scale Integration (VLSI) Systems p.2976-2980
Abstract
This brief presents an on-chip memory subsystem for massive multiple-input-multiple-output (MIMO) baseband processing at the base station. In massive MIMO systems, the required memory bandwidth and capacity are orders of magnitude higher than those used in conventional wireless systems, due to the large number of serving antennas. These are further combined with design targets on low access latency and flexibility in data organization and access modes. This brief applies and improves the concept of parallel memories to achieve the challenging design target with low hardware overhead. As a case study, a memory subsystem for 128-antenna and 16-user massive MIMO systems is evaluated using ST 28-nm technology. According to postlayout... (More)
This brief presents an on-chip memory subsystem for massive multiple-input-multiple-output (MIMO) baseband processing at the base station. In massive MIMO systems, the required memory bandwidth and capacity are orders of magnitude higher than those used in conventional wireless systems, due to the large number of serving antennas. These are further combined with design targets on low access latency and flexibility in data organization and access modes. This brief applies and improves the concept of parallel memories to achieve the challenging design target with low hardware overhead. As a case study, a memory subsystem for 128-antenna and 16-user massive MIMO systems is evaluated using ST 28-nm technology. According to postlayout simulation results, the proposed memory subsystem provides 512-Gb/s throughput and offers 1-Mb capacity with a cost of 0.30 mm2. (Less)
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author
organization
publishing date
type
Contribution to journal
publication status
published
subject
in
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
pages
2976 - 2980
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85028977791
  • wos:000413751500027
ISSN
1063-8210
DOI
10.1109/TVLSI.2017.2732062
language
English
LU publication?
yes
id
9d4ec7a8-fd92-41a0-a339-9d39c0102d2a
date added to LUP
2017-08-09 17:57:24
date last changed
2018-01-16 13:22:29
@article{9d4ec7a8-fd92-41a0-a339-9d39c0102d2a,
  abstract     = {This brief presents an on-chip memory subsystem for massive multiple-input-multiple-output (MIMO) baseband processing at the base station. In massive MIMO systems, the required memory bandwidth and capacity are orders of magnitude higher than those used in conventional wireless systems, due to the large number of serving antennas. These are further combined with design targets on low access latency and flexibility in data organization and access modes. This brief applies and improves the concept of parallel memories to achieve the challenging design target with low hardware overhead. As a case study, a memory subsystem for 128-antenna and 16-user massive MIMO systems is evaluated using ST 28-nm technology. According to postlayout simulation results, the proposed memory subsystem provides 512-Gb/s throughput and offers 1-Mb capacity with a cost of 0.30 mm2.},
  author       = {Liu, Yangxurui and Liu, Liang and Öwall, Viktor},
  issn         = {1063-8210},
  language     = {eng},
  pages        = {2976--2980},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  title        = {Architecture Design of a Memory Subsystem for Massive MIMO Baseband Processing},
  url          = {http://dx.doi.org/10.1109/TVLSI.2017.2732062},
  year         = {2017},
}