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A 13 Gbps, 0.13 μm CMOS, Multiplication-Free MIMO Detector

Mahdavi, Mojtaba LU and Shabany, Mahdi (2016) In Journal of Signal Processing Systems p.1-13
Abstract
A novel ultra high-throughput detection algorithm with an efficient VLSI architecture for high-order MIMO detectors in the complex constellations is proposed. The main contributions include a new method for the node generation in complex-domain, pipelinable sorters, and a simple combinational circuit instead of the conventional multipliers, which makes the proposed architecture multiplication-free. The proposed design achieves an SNR-independent throughput of 13.3 Gbps at the clock frequency of 556 MHz in a 0.13 μm CMOS technology with a near ML performance. The implemented design consumes 90 pJ per detected bit with the initial latency of 0.3 μs. Also, the synthesis results in a 90 nm CMOS technology prove that the proposed design can... (More)
A novel ultra high-throughput detection algorithm with an efficient VLSI architecture for high-order MIMO detectors in the complex constellations is proposed. The main contributions include a new method for the node generation in complex-domain, pipelinable sorters, and a simple combinational circuit instead of the conventional multipliers, which makes the proposed architecture multiplication-free. The proposed design achieves an SNR-independent throughput of 13.3 Gbps at the clock frequency of 556 MHz in a 0.13 μm CMOS technology with a near ML performance. The implemented design consumes 90 pJ per detected bit with the initial latency of 0.3 μs. Also, the synthesis results in a 90 nm CMOS technology prove that the proposed design can achieve the throughput of 20 Gbps. Moreover, an FPGA platform was developed using a Xilinx ML605 Evaluation board, demonstrating a sustained throughput of 3.3 Gbps at 140 MHz clock frequency. As an important feature, the proposed architecture can easily be extended to higher-order constellations and can be tailored for low-power/lower-area applications at the expense of a lower detection throughput. “A less efficient flavor of the algorithm presented in this paper, was presented in part in [10]. The proposed design in this paper has improved significantly in terms of the proposed algorithm, architecture, the basic blocks, and the final implementation results while presenting comprehensive complexity analysis of the proposed method. (Less)
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author
publishing date
type
Contribution to journal
publication status
published
subject
in
Journal of Signal Processing Systems
pages
13 pages
publisher
Springer
external identifiers
  • scopus:85024921348
ISSN
1939-8115
DOI
10.1007/s11265-016-1145-2
language
English
LU publication?
no
id
a08a9afa-af67-48ba-b8b7-b4eae8eff201
date added to LUP
2016-12-24 15:36:16
date last changed
2017-10-01 05:28:05
@article{a08a9afa-af67-48ba-b8b7-b4eae8eff201,
  abstract     = {A novel ultra high-throughput detection algorithm with an efficient VLSI architecture for high-order MIMO detectors in the complex constellations is proposed. The main contributions include a new method for the node generation in complex-domain, pipelinable sorters, and a simple combinational circuit instead of the conventional multipliers, which makes the proposed architecture multiplication-free. The proposed design achieves an SNR-independent throughput of 13.3 Gbps at the clock frequency of 556 MHz in a 0.13 μm CMOS technology with a near ML performance. The implemented design consumes 90 pJ per detected bit with the initial latency of 0.3 μs. Also, the synthesis results in a 90 nm CMOS technology prove that the proposed design can achieve the throughput of 20 Gbps. Moreover, an FPGA platform was developed using a Xilinx ML605 Evaluation board, demonstrating a sustained throughput of 3.3 Gbps at 140 MHz clock frequency. As an important feature, the proposed architecture can easily be extended to higher-order constellations and can be tailored for low-power/lower-area applications at the expense of a lower detection throughput. “A less efficient flavor of the algorithm presented in this paper, was presented in part in [10]. The proposed design in this paper has improved significantly in terms of the proposed algorithm, architecture, the basic blocks, and the final implementation results while presenting comprehensive complexity analysis of the proposed method.},
  author       = {Mahdavi, Mojtaba and Shabany, Mahdi},
  issn         = {1939-8115},
  language     = {eng},
  month        = {06},
  pages        = {1--13},
  publisher    = {Springer},
  series       = {Journal of Signal Processing Systems},
  title        = {A 13 Gbps, 0.13 μm CMOS, Multiplication-Free MIMO Detector},
  url          = {http://dx.doi.org/10.1007/s11265-016-1145-2},
  year         = {2016},
}