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A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers

Ek, Staffan; Pahlsson, Tony; Elgaard, Christian LU ; Carlsson, Anders; Axholt, Andreas LU ; Stenman, Anna Karin; Sundstrom, Lars and Sjoland, Henrik LU (2018) In IEEE Journal of Solid-State Circuits 53(7). p.1988-2000
Abstract

A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-antenna transceivers is presented. The system is modular with one phase locked loop (PLL) per antenna element transceiver, and a test circuit implemented in 28-nm fully depleted silicon on insulator (FD-SOI) CMOS features two such PLLs and a 491.52 MHz crystal oscillator (XO) generating a common frequency reference. A fractional-N architecture is employed to achieve high-frequency resolution, and the quantization noise is reduced using a novel frequency divider, which achieves full integer resolution while still using a pre-scaler. The system covers the 3rd Generation Partnership Project (3GPP) bands n257 and n258, achieved by a digital coarse tuning... (More)

A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-antenna transceivers is presented. The system is modular with one phase locked loop (PLL) per antenna element transceiver, and a test circuit implemented in 28-nm fully depleted silicon on insulator (FD-SOI) CMOS features two such PLLs and a 491.52 MHz crystal oscillator (XO) generating a common frequency reference. A fractional-N architecture is employed to achieve high-frequency resolution, and the quantization noise is reduced using a novel frequency divider, which achieves full integer resolution while still using a pre-scaler. The system covers the 3rd Generation Partnership Project (3GPP) bands n257 and n258, achieved by a digital coarse tuning of the voltage-controlled oscillator (VCO). The chip area of each PLL is 0.11 mm², and 0.029 mm² for the XO. The total power consumption of the system is 35 mW, where each PLL consumes 15.4 mW and the XO consumes 0.84 mW. The total rms jitter from 20-kHz to 500-MHz offset for a 26-GHz carrier is just 115 fs, corresponding to an FOMj of -244 dB, which is the best reported figure for a fractional-N PLL above 15 GHz. The error-vector magnitude (EVM) due to phase noise is -34.6 dBc using an orthogonal frequency-division multiplexing (OFDM) signal with 120-kHz sub-carrier spacing, sufficient to support 256 QAM.

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Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
5G mobile communication, CMOS, crystal oscillator (XO), decorrelation, delta-sigma modulator (DSM), fifth generation (5G), fractional-N, Frequency conversion, frequency synthesis, millimeter-wave (mmW), OFDM, Phase locked loops, Phase noise, phase noise, phase-locked loops (PLLs), radio transceivers., Transceivers, Voltage-controlled oscillators
in
IEEE Journal of Solid-State Circuits
volume
53
issue
7
pages
1988 - 2000
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85045727464
ISSN
0018-9200
DOI
10.1109/JSSC.2018.2820149
language
English
LU publication?
yes
id
a2a517b4-a874-446c-ab14-120fa846d52e
date added to LUP
2018-05-23 10:18:22
date last changed
2019-01-14 14:36:54
@article{a2a517b4-a874-446c-ab14-120fa846d52e,
  abstract     = {<p>A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-antenna transceivers is presented. The system is modular with one phase locked loop (PLL) per antenna element transceiver, and a test circuit implemented in 28-nm fully depleted silicon on insulator (FD-SOI) CMOS features two such PLLs and a 491.52 MHz crystal oscillator (XO) generating a common frequency reference. A fractional-N architecture is employed to achieve high-frequency resolution, and the quantization noise is reduced using a novel frequency divider, which achieves full integer resolution while still using a pre-scaler. The system covers the 3rd Generation Partnership Project (3GPP) bands n257 and n258, achieved by a digital coarse tuning of the voltage-controlled oscillator (VCO). The chip area of each PLL is 0.11 mm&amp;#x00B2;, and 0.029 mm&amp;#x00B2; for the XO. The total power consumption of the system is 35 mW, where each PLL consumes 15.4 mW and the XO consumes 0.84 mW. The total rms jitter from 20-kHz to 500-MHz offset for a 26-GHz carrier is just 115 fs, corresponding to an FOMj of -244 dB, which is the best reported figure for a fractional-N PLL above 15 GHz. The error-vector magnitude (EVM) due to phase noise is -34.6 dBc using an orthogonal frequency-division multiplexing (OFDM) signal with 120-kHz sub-carrier spacing, sufficient to support 256 QAM.</p>},
  author       = {Ek, Staffan and Pahlsson, Tony and Elgaard, Christian and Carlsson, Anders and Axholt, Andreas and Stenman, Anna Karin and Sundstrom, Lars and Sjoland, Henrik},
  issn         = {0018-9200},
  keyword      = {5G mobile communication,CMOS,crystal oscillator (XO),decorrelation,delta-sigma modulator (DSM),fifth generation (5G),fractional-N,Frequency conversion,frequency synthesis,millimeter-wave (mmW),OFDM,Phase locked loops,Phase noise,phase noise,phase-locked loops (PLLs),radio transceivers.,Transceivers,Voltage-controlled oscillators},
  language     = {eng},
  month        = {04},
  number       = {7},
  pages        = {1988--2000},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Journal of Solid-State Circuits},
  title        = {A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers},
  url          = {http://dx.doi.org/10.1109/JSSC.2018.2820149},
  volume       = {53},
  year         = {2018},
}