An Architecture for Combined Test Data Compression and Abort-on-Fail Test
Larsson, Erik LU
and Persson, Jon
(2007)
Asia and South Pacific Design Automation Conference ASP-DAC '07
p.726-731
- Abstract
- The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared... (More)
- The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (Multiple-Input Signature Register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X). (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/2341025
- author
- Larsson, Erik
LU
and Persson, Jon
- publishing date
- 2007
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- testing, electronic systems, test data compression, unknowns
- host publication
- [Host publication title missing]
- pages
- 726 - 731
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- Asia and South Pacific Design Automation Conference ASP-DAC '07
- conference location
- Yokohama, Japan
- conference dates
- 2007-01-23 - 2007-01-26
- external identifiers
-
- scopus:45849089249
- ISBN
- 1-4244-0629-3
- DOI
- 10.1109/ASPDAC.2007.358073
- language
- English
- LU publication?
- no
- id
- af3de971-0db5-4654-9bfa-e919e8f675ee (old id 2341025)
- date added to LUP
- 2016-04-04 10:03:39
- date last changed
- 2022-02-13 19:13:34
@inproceedings{af3de971-0db5-4654-9bfa-e919e8f675ee,
abstract = {{The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and long test application times. In contrast to previous approaches that address either test data compression or abort-on-fail testing, we propose an architecture for combined test data compression and abort-on-fail testing. The architecture improves throughput through multi-site testing as the ATE memory requirement is constant and independent of the degree of multi-site testing. For flexibility in modifying the test data at any time, we make use of a test program for decompression; only test independent evaluation logic is added to the IC. Major advantages compared to MISR (Multiple-Input Signature Register) based schemes are that our scheme (1) allows abort-on-fail testing at clock-cycle granularity, (2) does not impact diagnostic capabilities, and (3) needs no special care for the handling of unknowns (X).}},
author = {{Larsson, Erik and Persson, Jon}},
booktitle = {{[Host publication title missing]}},
isbn = {{1-4244-0629-3}},
keywords = {{testing; electronic systems; test data compression; unknowns}},
language = {{eng}},
pages = {{726--731}},
publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
title = {{An Architecture for Combined Test Data Compression and Abort-on-Fail Test}},
url = {{http://dx.doi.org/10.1109/ASPDAC.2007.358073}},
doi = {{10.1109/ASPDAC.2007.358073}},
year = {{2007}},
}