Advanced

An Efficient VLSI Architecture of QPP Interleaver/deinterleaver for LTE Turbo Coding

Ardakani, Arash ; Mahdavi, Mojtaba LU and Shabany, Mahdi (2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 In IEEE International Symposium on Circuits and Systems (ISCAS), 2013 p.797-800
Abstract
Abstract:
Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design requires no memory or QPP inverse... (More)
Abstract:
Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design requires no memory or QPP inverse to perform deinterleaving and has been fully implemented and tested both on a Virtex-6 FPGA as well as in a 0.18 um CMOS process. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
IEEE International Symposium on Circuits and Systems (ISCAS), 2013
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2013
external identifiers
  • scopus:84883319808
ISBN
978-1-4673-5760-9
978-1-4673-5762-3
DOI
10.1109/ISCAS.2013.6571967
language
English
LU publication?
no
id
b2eab531-41d3-4b0e-a5ab-5f36b68c55e2
date added to LUP
2016-12-24 17:37:02
date last changed
2018-05-29 09:50:17
@inproceedings{b2eab531-41d3-4b0e-a5ab-5f36b68c55e2,
  abstract     = {Abstract: <br/>Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design requires no memory or QPP inverse to perform deinterleaving and has been fully implemented and tested both on a Virtex-6 FPGA as well as in a 0.18 um CMOS process.},
  author       = {Ardakani, Arash  and Mahdavi, Mojtaba and Shabany, Mahdi},
  booktitle    = {IEEE International Symposium on Circuits and Systems (ISCAS), 2013},
  isbn         = {978-1-4673-5760-9},
  language     = {eng},
  month        = {08},
  pages        = {797--800},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {An Efficient VLSI Architecture of QPP Interleaver/deinterleaver for LTE Turbo Coding},
  url          = {http://dx.doi.org/10.1109/ISCAS.2013.6571967},
  year         = {2013},
}