Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

A Decade Frequency Range CMOS Power Amplifier for Sub-6-GHz Cellular Terminals

Lindstrand, Jonas LU ; Tormanen, Markus LU orcid and Sjoland, Henrik LU orcid (2020) In IEEE Microwave and Wireless Components Letters 30(1). p.54-57
Abstract

A wideband 65-nm CMOS power amplifier (PA) is presented, with a decade frequency range from 600 MHz to 6.0 GHz. In this frequency range, the output power exceeds 26.6 dBm and the power gain and power-added efficiency (PAE) exceed 18.1 dB and 49%, respectively. For a 7.5-dB peak-to-average-power-ratio (PAPR) long term evolution (LTE) signal at 1.9 GHz, the circuit provides an average output power of 19 dBm, with a PAE of 40%, and an adjacent channel leakage ratio (ACLR) exceeding -31 dBc. In LTE measurements at 5.9 GHz, the average output power, PAE, and ACLR are 18.5 dBm, 38.8%, and -30 dBc, respectively, using supply modulation and baseband predistortion. The wide bandwidth (BW) and high performance are achieved by introducing a dual... (More)

A wideband 65-nm CMOS power amplifier (PA) is presented, with a decade frequency range from 600 MHz to 6.0 GHz. In this frequency range, the output power exceeds 26.6 dBm and the power gain and power-added efficiency (PAE) exceed 18.1 dB and 49%, respectively. For a 7.5-dB peak-to-average-power-ratio (PAPR) long term evolution (LTE) signal at 1.9 GHz, the circuit provides an average output power of 19 dBm, with a PAE of 40%, and an adjacent channel leakage ratio (ACLR) exceeding -31 dBc. In LTE measurements at 5.9 GHz, the average output power, PAE, and ACLR are 18.5 dBm, 38.8%, and -30 dBc, respectively, using supply modulation and baseband predistortion. The wide bandwidth (BW) and high performance are achieved by introducing a dual output topology with an off-chip higher order output-matching network, combined with a positive feedback cross-coupled differential cascode amplifier stage. By using supply modulation and dynamic gate bias with an injection-locked PA, improved back-off efficiency, and acceptable out-of-band and in-band distortion is obtained. The integrated circuit occupies an area of 1.0 \times 0.73 mm2 in standard 65-nm CMOS technology and uses a supply of 3.0 V.

(Less)
Please use this url to cite or link to this publication:
author
; and
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
Broadband, CMOS, dynamic biasing, efficiency, injection lock, long term evolution (LTE), multiband, power amplifier (PA)
in
IEEE Microwave and Wireless Components Letters
volume
30
issue
1
article number
8933336
pages
4 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85078528364
ISSN
1531-1309
DOI
10.1109/LMWC.2019.2955602
language
English
LU publication?
yes
id
c5226a9b-08f2-45e4-8105-f388e8ccd5cd
date added to LUP
2020-02-10 12:11:47
date last changed
2024-02-16 09:48:43
@article{c5226a9b-08f2-45e4-8105-f388e8ccd5cd,
  abstract     = {{<p>A wideband 65-nm CMOS power amplifier (PA) is presented, with a decade frequency range from 600 MHz to 6.0 GHz. In this frequency range, the output power exceeds 26.6 dBm and the power gain and power-added efficiency (PAE) exceed 18.1 dB and 49%, respectively. For a 7.5-dB peak-to-average-power-ratio (PAPR) long term evolution (LTE) signal at 1.9 GHz, the circuit provides an average output power of 19 dBm, with a PAE of 40%, and an adjacent channel leakage ratio (ACLR) exceeding -31 dBc. In LTE measurements at 5.9 GHz, the average output power, PAE, and ACLR are 18.5 dBm, 38.8%, and -30 dBc, respectively, using supply modulation and baseband predistortion. The wide bandwidth (BW) and high performance are achieved by introducing a dual output topology with an off-chip higher order output-matching network, combined with a positive feedback cross-coupled differential cascode amplifier stage. By using supply modulation and dynamic gate bias with an injection-locked PA, improved back-off efficiency, and acceptable out-of-band and in-band distortion is obtained. The integrated circuit occupies an area of 1.0 \times 0.73 mm<sup>2</sup> in standard 65-nm CMOS technology and uses a supply of 3.0 V.</p>}},
  author       = {{Lindstrand, Jonas and Tormanen, Markus and Sjoland, Henrik}},
  issn         = {{1531-1309}},
  keywords     = {{Broadband; CMOS; dynamic biasing; efficiency; injection lock; long term evolution (LTE); multiband; power amplifier (PA)}},
  language     = {{eng}},
  number       = {{1}},
  pages        = {{54--57}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  series       = {{IEEE Microwave and Wireless Components Letters}},
  title        = {{A Decade Frequency Range CMOS Power Amplifier for Sub-6-GHz Cellular Terminals}},
  url          = {{http://dx.doi.org/10.1109/LMWC.2019.2955602}},
  doi          = {{10.1109/LMWC.2019.2955602}},
  volume       = {{30}},
  year         = {{2020}},
}