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An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping

Karami, Poorya ; Banaeikashani, Amirali ; Behmanesh, Baktash LU and Atarodi, Seyed Mojtaba (2020) In IEEE Transactions on Circuits and Systems I: Regular Papers
Abstract

In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is reduced by a factor of n. As a proof of concept, a... (More)

In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is reduced by a factor of n. As a proof of concept, a 0.1-5 GHz RF filter with 75 dB and 82 dB harmonic rejection at 3rd and 5th order harmonics respectively is analyzed and simulated using MATLAB and Cadence Spectre-RF. Post-layout simulations are performed using CMOS 180 nm technology with 1.8 V supply voltage. The total power consumption of the chip is less than 8.5 mW while occupying a silicon area of 0.2 mm². Furthermore, Noise Figure (NF) of the circuit is shown to be between 3.5 and 4.7 dB and its out-of-band IIP3 is +6 dBm.

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type
Contribution to journal
publication status
published
subject
keywords
Band-pass filter, Band-pass filters, Baseband, Clocks, CMOS, cognitive radio, frequency folding, Generators, Harmonic analysis, harmonic free, high-Q, N-path filter, power consumption, Power harmonic filters, software defined radio (SDR), tunable filter.
in
IEEE Transactions on Circuits and Systems I: Regular Papers
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:85089298484
ISSN
1549-8328
DOI
10.1109/TCSI.2020.3009191
language
English
LU publication?
yes
id
c618067f-1df8-4585-a1ae-fde514ce6f93
date added to LUP
2020-08-19 13:50:29
date last changed
2020-12-29 02:26:49
@article{c618067f-1df8-4585-a1ae-fde514ce6f93,
  abstract     = {<p>In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is reduced by a factor of n. As a proof of concept, a 0.1-5 GHz RF filter with 75 dB and 82 dB harmonic rejection at 3rd and 5th order harmonics respectively is analyzed and simulated using MATLAB and Cadence Spectre-RF. Post-layout simulations are performed using CMOS 180 nm technology with 1.8 V supply voltage. The total power consumption of the chip is less than 8.5 mW while occupying a silicon area of 0.2 mm&amp;#x00B2;. Furthermore, Noise Figure (NF) of the circuit is shown to be between 3.5 and 4.7 dB and its out-of-band IIP3 is +6 dBm.</p>},
  author       = {Karami, Poorya and Banaeikashani, Amirali and Behmanesh, Baktash and Atarodi, Seyed Mojtaba},
  issn         = {1549-8328},
  language     = {eng},
  publisher    = {IEEE - Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Transactions on Circuits and Systems I: Regular Papers},
  title        = {An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping},
  url          = {http://dx.doi.org/10.1109/TCSI.2020.3009191},
  doi          = {10.1109/TCSI.2020.3009191},
  year         = {2020},
}