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A unified approach to constrained mapping and routing on network-on-chip architectures

Hansson, A ; Goossens, K and Radulescu, A (2005) International Conference on Hardware/Software Codesign and System Synthesis p.75-80
Abstract
One of the key steps in network-on-chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called unified mapping, routing and slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of... (More)
One of the key steps in network-on-chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called unified mapping, routing and slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach (Less)
Please use this url to cite or link to this publication:
author
; and
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
MPEG decoder system-on-chip, TDMA time-slot allocation, slot allocation, network routing, unified mapping, route communication, spatial mapping, constrained mapping, network-on-chip architectures
host publication
International Conference on Hardware/Software Codesign and System Synthesis (IEEE Cat. No. 05TH8852)
pages
75 - 80
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
International Conference on Hardware/Software Codesign and System Synthesis
conference location
Jersey City, NJ, United States
conference dates
2005-09-18 - 2005-09-21
external identifiers
  • wos:000233237900014
  • scopus:27644490224
ISBN
1-59593-161-9
DOI
10.1145/1084834.1084857
language
English
LU publication?
no
id
d52569dc-202e-4b34-afbb-0b55f21fbf1c (old id 615676)
date added to LUP
2016-04-04 12:05:45
date last changed
2022-04-24 01:34:14
@inproceedings{d52569dc-202e-4b34-afbb-0b55f21fbf1c,
  abstract     = {{One of the key steps in network-on-chip (NoC) based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problem first map cores onto a topology and then route communication, using separated and possibly conflicting objective functions. In this paper we present a unified single-objective algorithm, called unified mapping, routing and slot allocation (UMARS). As the main contribution we show how to couple path selection, mapping of cores and TDMA time-slot allocation such that the network required to meet the constraints of the application is minimized. The time-complexity of UMARS is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder system-on-chip (SoC), reducing area by 33%, power by 35% and worst-case latency by a factor four over a traditional multi-step approach}},
  author       = {{Hansson, A and Goossens, K and Radulescu, A}},
  booktitle    = {{International Conference on Hardware/Software Codesign and System Synthesis (IEEE Cat. No. 05TH8852)}},
  isbn         = {{1-59593-161-9}},
  keywords     = {{MPEG decoder system-on-chip; TDMA time-slot allocation; slot allocation; network routing; unified mapping; route communication; spatial mapping; constrained mapping; network-on-chip architectures}},
  language     = {{eng}},
  pages        = {{75--80}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{A unified approach to constrained mapping and routing on network-on-chip architectures}},
  url          = {{http://dx.doi.org/10.1145/1084834.1084857}},
  doi          = {{10.1145/1084834.1084857}},
  year         = {{2005}},
}