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Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC

Westring, Kristoffer LU and Svensson, Linus LU (2023)
Abstract
The recent peak in interest for artificial intelligence, partly fueled by language
models such as ChatGPT, is pushing the demand for machine learning and data
processing in everyday applications, such as self-driving cars, where low latency is
crucial and typically achieved through edge computing. The vast amount of data
processing required intensifies the existing performance bottleneck of the data
movement. As a result, reducing data movement and allowing for better data
reuse can significantly improve the efficiency.
Processing the data as closely to the memory as possible, commonly known as
near-memory computing, increases the power efficiency and can significantly re-
duce the bottleneck in the data... (More)
The recent peak in interest for artificial intelligence, partly fueled by language
models such as ChatGPT, is pushing the demand for machine learning and data
processing in everyday applications, such as self-driving cars, where low latency is
crucial and typically achieved through edge computing. The vast amount of data
processing required intensifies the existing performance bottleneck of the data
movement. As a result, reducing data movement and allowing for better data
reuse can significantly improve the efficiency.
Processing the data as closely to the memory as possible, commonly known as
near-memory computing, increases the power efficiency and can significantly re-
duce the bottleneck in the data movement. However, maintaining a low power
consumption while at the same time being able to process large amounts of data
is a challenge. The RISC-V Instruction Set Architecture (ISA) was designed for
efficient and dense instruction encoding, enabling lower power consumption and
quicker execution time. Extending the simple RISC-V ISA with specific instruc-
tions for applications like image recognition can make a processor energy-efficient
but less versatile than a conventional CISC processor. Codasip, a company
specializing in RISC-V processors, offers a toolset for exploring and customizing
processor architectures, through their proprietary C-based hardware description
language, CodAl, which is used to generate SDK, HDL, and UVM within the Co-
dasip Studio Environment. Codasip provides a selection fully configurable RISC-V
cores, tailored for either low-power, and high-performance application.
In this thesis we use a combination of high-level synthesis tools and EDA soft-
ware to simplify design space exploration of accelerators, allowing for the accel-
erators to be integrated as Near Memory Computing (NMC) accelerators on a
customized RISC-V System on chip (SoC), for both Application Specific Inte-
grated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA). The flow
contains implementation of custom instructions as well as a generic flow from
Register Transfer Level (RTL) to GDSII for reuse in future works (Less)
Please use this url to cite or link to this publication:
author
and
supervisor
organization
publishing date
type
Thesis
publication status
published
subject
pages
72 pages
publisher
Department of Electrical and Information Technology, Lund University
language
English
LU publication?
yes
id
df11d09e-68e8-4dea-8cd1-7930a64f4dc8
alternative location
https://lup.lub.lu.se/luur/download?func=downloadFile&recordOId=9140333&fileOId=9140398
date added to LUP
2024-02-09 13:08:17
date last changed
2024-02-13 09:34:38
@misc{df11d09e-68e8-4dea-8cd1-7930a64f4dc8,
  abstract     = {{The recent peak in interest for artificial intelligence, partly fueled by language<br/>models such as ChatGPT, is pushing the demand for machine learning and data<br/>processing in everyday applications, such as self-driving cars, where low latency is<br/>crucial and typically achieved through edge computing. The vast amount of data<br/>processing required intensifies the existing performance bottleneck of the data<br/>movement. As a result, reducing data movement and allowing for better data<br/>reuse can significantly improve the efficiency.<br/>Processing the data as closely to the memory as possible, commonly known as<br/>near-memory computing, increases the power efficiency and can significantly re-<br/>duce the bottleneck in the data movement. However, maintaining a low power<br/>consumption while at the same time being able to process large amounts of data<br/>is a challenge. The RISC-V Instruction Set Architecture (ISA) was designed for<br/>efficient and dense instruction encoding, enabling lower power consumption and<br/>quicker execution time. Extending the simple RISC-V ISA with specific instruc-<br/>tions for applications like image recognition can make a processor energy-efficient<br/>but less versatile than a conventional CISC processor. Codasip, a company<br/>specializing in RISC-V processors, offers a toolset for exploring and customizing<br/>processor architectures, through their proprietary C-based hardware description<br/>language, CodAl, which is used to generate SDK, HDL, and UVM within the Co-<br/>dasip Studio Environment. Codasip provides a selection fully configurable RISC-V<br/>cores, tailored for either low-power, and high-performance application.<br/>In this thesis we use a combination of high-level synthesis tools and EDA soft-<br/>ware to simplify design space exploration of accelerators, allowing for the accel-<br/>erators to be integrated as Near Memory Computing (NMC) accelerators on a<br/>customized RISC-V System on chip (SoC), for both Application Specific Inte-<br/>grated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA). The flow<br/>contains implementation of custom instructions as well as a generic flow from<br/>Register Transfer Level (RTL) to GDSII for reuse in future works}},
  author       = {{Westring, Kristoffer and Svensson, Linus}},
  language     = {{eng}},
  month        = {{10}},
  publisher    = {{Department of Electrical and Information Technology, Lund University}},
  title        = {{Low-power Acceleration of Convolutional Neural Networks using Near Memory Computing on a RISC-V SoC}},
  url          = {{https://lup.lub.lu.se/luur/download?func=downloadFile&recordOId=9140333&fileOId=9140398}},
  year         = {{2023}},
}