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Instruction Selection and Scheduling for DSP Kernels on Custom Architectures

Arslan, Mehmet Ali LU and Kuchcinski, Krzysztof LU orcid (2013) 16th Euromicro conference on Digital System Design p.821-828
Abstract
As custom architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modelling, while state-of-the-art constraint solvers enable optimal... (More)
As custom architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modelling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation. (Less)
Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
embedded, constraint programming, design space exploration, instruction scheduling, instruction selection
host publication
16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013)
pages
8 pages
publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
conference name
16th Euromicro conference on Digital System Design
conference location
Santander, Spain
conference dates
2013-09-04
external identifiers
  • wos:000337235200114
  • scopus:84890026072
ISBN
978-0-7695-5074-9
DOI
10.1109/DSD.2013.91
project
High Performance Embedded Computing
language
English
LU publication?
yes
id
e5baf798-9bdf-4c16-b5e1-44ace441402d (old id 3972673)
date added to LUP
2016-04-04 11:10:31
date last changed
2022-02-28 19:30:29
@inproceedings{e5baf798-9bdf-4c16-b5e1-44ace441402d,
  abstract     = {{As custom architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modelling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation.}},
  author       = {{Arslan, Mehmet Ali and Kuchcinski, Krzysztof}},
  booktitle    = {{16TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2013)}},
  isbn         = {{978-0-7695-5074-9}},
  keywords     = {{embedded; constraint programming; design space exploration; instruction scheduling; instruction selection}},
  language     = {{eng}},
  pages        = {{821--828}},
  publisher    = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}},
  title        = {{Instruction Selection and Scheduling for DSP Kernels on Custom Architectures}},
  url          = {{https://lup.lub.lu.se/search/files/5711613/3972678.pdf}},
  doi          = {{10.1109/DSD.2013.91}},
  year         = {{2013}},
}