Analog-to-Digital Converters for High-Speed Applications
(2024)- Abstract
- This thesis delves into the multifaceted challenges of designing analog-to-digital converters (ADCs) tailored for high-speed and medium accuracy applications, particularly in deeply scaled-down CMOS technologies across five comprehensive chapters within its Introduction. Furthermore, it explores the evolution of mobile telephony from the first-generation (1G) to the last commercialized generation and beyond, highlighting the pivotal role of data converters in modern communication systems.
This journey continues to the second chapter where the intricate processes of sampling and quantization from theoretical concepts to practical implementations is covered, clarifying the hurdles encountered in achieving superior performance. In this... (More) - This thesis delves into the multifaceted challenges of designing analog-to-digital converters (ADCs) tailored for high-speed and medium accuracy applications, particularly in deeply scaled-down CMOS technologies across five comprehensive chapters within its Introduction. Furthermore, it explores the evolution of mobile telephony from the first-generation (1G) to the last commercialized generation and beyond, highlighting the pivotal role of data converters in modern communication systems.
This journey continues to the second chapter where the intricate processes of sampling and quantization from theoretical concepts to practical implementations is covered, clarifying the hurdles encountered in achieving superior performance. In this chapter, a comprehensive analysis of the bootstrapped switch is discussed, addressing its design considerations, challenges, and techniques to achieve optimal linearity by addressing the errors introduced during its phase change. Furthermore, quantization process is explored with focus on the pivotal role of the comparators in the linearity and speed of the converter, followed by a brief review on the published techniques to improve their performance.
This exploration extends into Chapter 3, which examines Nyquist rate ADC architectures, including successive approximation register (SAR), flash, and pipeline ADCs. Through a comparative analysis, it discusses their respective complexities, speeds, and accuracies, guiding designers in optimal selection and refinement for specific applications. Through this lens, it compares their advantages, disadvantages, and the impact of technological scaling on their speed and resolution.
Chapter 4 unfolds the design intricacies of time-interleaved (TI) pipelined-SAR ADCs, underscoring the indispensable role of time interleaving in boosting speed and power efficiency. Moreover, it delves into the challenges and advantages of pipelined-SAR ADCs, accompanied by insights into the measurement test bench utilized to evaluate performance, thus bridging theoretical discourse with practical application.
Conclusively, the Introduction part briefs the challenges, achievements, and contributions of the thesis, offering insights and recommendations for future research trajectories in the realm of high-speed ADC design.
Moreover, the thesis ventures into five original papers in its second part, discussing multiple designs and leveraging techniques such as time interleaving, employment of hybrid ADCs, and asynchronous clocking to attain superior performance metrics encompassing speed, resolution, and power efficiency.
Notable contributions include techniques to enhance BST-SW linearity, the design of a high-speed comparator, synchronous versus asynchronous SAR ADC comparison and implementation of a 4-channel TI pipelined-SAR ADC in a 22-nm FDSOI CMOS process, capable of operating at a sampling rate of 1.4 GS/s.
(Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/eddbafe8-1606-42e2-aed1-0e3c818ebe26
- author
- Karrari, Hamid LU
- opponent
-
- Prof. Murmann, Boris, University of Hawaii, USA.
- organization
- publishing date
- 2024
- type
- Thesis
- publication status
- published
- subject
- pages
- 173 pages
- publisher
- Department of Electrical and Information Technology, Lund University
- defense location
- Lecture Hall E:1406, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund. The dissertation will be live streamed, but part of the premises is to be excluded from the live stream.
- defense date
- 2024-06-14 09:15:00
- ISBN
- 978-91-8104-091-3
- 978-91-8104-092-0
- language
- English
- LU publication?
- yes
- id
- eddbafe8-1606-42e2-aed1-0e3c818ebe26
- date added to LUP
- 2024-05-20 13:43:49
- date last changed
- 2024-05-21 12:25:42
@phdthesis{eddbafe8-1606-42e2-aed1-0e3c818ebe26,
abstract = {{This thesis delves into the multifaceted challenges of designing analog-to-digital converters (ADCs) tailored for high-speed and medium accuracy applications, particularly in deeply scaled-down CMOS technologies across five comprehensive chapters within its Introduction. Furthermore, it explores the evolution of mobile telephony from the first-generation (1G) to the last commercialized generation and beyond, highlighting the pivotal role of data converters in modern communication systems.<br/>This journey continues to the second chapter where the intricate processes of sampling and quantization from theoretical concepts to practical implementations is covered, clarifying the hurdles encountered in achieving superior performance. In this chapter, a comprehensive analysis of the bootstrapped switch is discussed, addressing its design considerations, challenges, and techniques to achieve optimal linearity by addressing the errors introduced during its phase change. Furthermore, quantization process is explored with focus on the pivotal role of the comparators in the linearity and speed of the converter, followed by a brief review on the published techniques to improve their performance.<br/>This exploration extends into Chapter 3, which examines Nyquist rate ADC architectures, including successive approximation register (SAR), flash, and pipeline ADCs. Through a comparative analysis, it discusses their respective complexities, speeds, and accuracies, guiding designers in optimal selection and refinement for specific applications. Through this lens, it compares their advantages, disadvantages, and the impact of technological scaling on their speed and resolution.<br/>Chapter 4 unfolds the design intricacies of time-interleaved (TI) pipelined-SAR ADCs, underscoring the indispensable role of time interleaving in boosting speed and power efficiency. Moreover, it delves into the challenges and advantages of pipelined-SAR ADCs, accompanied by insights into the measurement test bench utilized to evaluate performance, thus bridging theoretical discourse with practical application.<br/>Conclusively, the Introduction part briefs the challenges, achievements, and contributions of the thesis, offering insights and recommendations for future research trajectories in the realm of high-speed ADC design.<br/>Moreover, the thesis ventures into five original papers in its second part, discussing multiple designs and leveraging techniques such as time interleaving, employment of hybrid ADCs, and asynchronous clocking to attain superior performance metrics encompassing speed, resolution, and power efficiency.<br/>Notable contributions include techniques to enhance BST-SW linearity, the design of a high-speed comparator, synchronous versus asynchronous SAR ADC comparison and implementation of a 4-channel TI pipelined-SAR ADC in a 22-nm FDSOI CMOS process, capable of operating at a sampling rate of 1.4 GS/s.<br/>}},
author = {{Karrari, Hamid}},
isbn = {{978-91-8104-091-3}},
language = {{eng}},
publisher = {{Department of Electrical and Information Technology, Lund University}},
school = {{Lund University}},
title = {{Analog-to-Digital Converters for High-Speed Applications}},
url = {{https://lup.lub.lu.se/search/files/183800236/Thesis_Hamid_Final_Revised_Signed.pdf}},
year = {{2024}},
}