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Investigating hardware micro-instruction folding in a Java embedded processor

Gruian, Flavius LU orcid and Westmijze, Mark (2010) p.102-108
Abstract
Bytecode folding is an effective technique for speeding up execution in Java virtual machines. This paper investigates a hardware implementation of the aforementioned technique on BlueJEP, a Java embedded processor. Since BlueJEP is a micro-programmed stack machine, we adopt a micro-instruction oriented approach, folding up to four microinstructions (corresponding to up to four bytecodes, on occasion). A variety of processor versions for different subsets of folding patterns are implemented, simulated and synthesized on a Xilinx FPGA. The measurements and results show that, although the number of execution cycles is reduced, the critical path increase leads to a lower performance. Taking into account the device area, we conclude that for... (More)
Bytecode folding is an effective technique for speeding up execution in Java virtual machines. This paper investigates a hardware implementation of the aforementioned technique on BlueJEP, a Java embedded processor. Since BlueJEP is a micro-programmed stack machine, we adopt a micro-instruction oriented approach, folding up to four microinstructions (corresponding to up to four bytecodes, on occasion). A variety of processor versions for different subsets of folding patterns are implemented, simulated and synthesized on a Xilinx FPGA. The measurements and results show that, although the number of execution cycles is reduced, the critical path increase leads to a lower performance. Taking into account the device area, we conclude that for our case, adding a second processor may be preferred over hardware folding. In general, we observe that folding efficiency may only be evaluated properly on a real implementation, rather than using theoretical estimates, due to the increased complexity of the hardware. (Less)
Please use this url to cite or link to this publication:
author
and
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
Java, Embedded Systems, BlueJEP, Bytecode Folding
host publication
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
pages
102 - 108
publisher
Association for Computing Machinery (ACM)
external identifiers
  • scopus:77957951173
ISBN
978-1-4503-0122-0
DOI
10.1145/1850771.1850787
language
English
LU publication?
yes
id
ee4a67c1-d8da-450f-b298-380483187d9d (old id 1660561)
date added to LUP
2016-04-04 10:58:11
date last changed
2025-10-14 11:58:12
@inproceedings{ee4a67c1-d8da-450f-b298-380483187d9d,
  abstract     = {{Bytecode folding is an effective technique for speeding up execution in Java virtual machines. This paper investigates a hardware implementation of the aforementioned technique on BlueJEP, a Java embedded processor. Since BlueJEP is a micro-programmed stack machine, we adopt a micro-instruction oriented approach, folding up to four microinstructions (corresponding to up to four bytecodes, on occasion). A variety of processor versions for different subsets of folding patterns are implemented, simulated and synthesized on a Xilinx FPGA. The measurements and results show that, although the number of execution cycles is reduced, the critical path increase leads to a lower performance. Taking into account the device area, we conclude that for our case, adding a second processor may be preferred over hardware folding. In general, we observe that folding efficiency may only be evaluated properly on a real implementation, rather than using theoretical estimates, due to the increased complexity of the hardware.}},
  author       = {{Gruian, Flavius and Westmijze, Mark}},
  booktitle    = {{Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems}},
  isbn         = {{978-1-4503-0122-0}},
  keywords     = {{Java; Embedded Systems; BlueJEP; Bytecode Folding}},
  language     = {{eng}},
  pages        = {{102--108}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{Investigating hardware micro-instruction folding in a Java embedded processor}},
  url          = {{http://dx.doi.org/10.1145/1850771.1850787}},
  doi          = {{10.1145/1850771.1850787}},
  year         = {{2010}},
}