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A framework to generate domain-specific manycore architectures from dataflow programs

Savas, Süleyman LU ; Ul-Abdin, Zain and Nordström, Tomas (2020) In Microprocessors and Microsystems 72.
Abstract

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures. However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method... (More)

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures. However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture. We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.

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author
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organization
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type
Contribution to journal
publication status
published
subject
keywords
Accelerator, Cal2many, Code generation, Domain-specific, Hardware/software co-design, Manycore, Multicore, Riscv, Rocket core, Rocketchip
in
Microprocessors and Microsystems
volume
72
article number
102908
publisher
Elsevier
external identifiers
  • scopus:85073496598
ISSN
0141-9331
DOI
10.1016/j.micpro.2019.102908
language
English
LU publication?
yes
id
f287dbd9-e76b-4755-b3b5-e71dc1c74340
date added to LUP
2019-10-25 08:47:25
date last changed
2020-10-07 06:45:12
@article{f287dbd9-e76b-4755-b3b5-e71dc1c74340,
  abstract     = {<p>In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures. However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture. We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.</p>},
  author       = {Savas, Süleyman and Ul-Abdin, Zain and Nordström, Tomas},
  issn         = {0141-9331},
  language     = {eng},
  publisher    = {Elsevier},
  series       = {Microprocessors and Microsystems},
  title        = {A framework to generate domain-specific manycore architectures from dataflow programs},
  url          = {http://dx.doi.org/10.1016/j.micpro.2019.102908},
  doi          = {10.1016/j.micpro.2019.102908},
  volume       = {72},
  year         = {2020},
}