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Logic filter cache for wide-VDD-range processors

Bardizbanyan, Alen; Andersson, Oskar LU ; Rodrigues, Joachim LU and Larsson-Edefors, Per (2017) 23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 In 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 p.376-379
Abstract

Wide-VDD-range processors offer high energy efficiency for varying embedded workloads. But reducing the VDD of the cache as aggressively as the VDD of the CPU logic is not straightforward, since standard 6T SRAMs cease to operate at lower VDDs. We implement a data and instruction filter cache, using logic cells located in the CPU VDD domain, to permit the level-1 (L1) cache to be reliably powered at a higher SRAM VDD. On top of eliminating many energy-wasting L1 cache accesses, the filter cache reduces the total number of executed cycles. Furthermore, the filter cache can be reconfigured as CPU VDD is reduced, to filter out an increasing proportion of cache accesses. We evaluate our approach using a 65-nm 1.2-V low-leakage CMOS process,... (More)

Wide-VDD-range processors offer high energy efficiency for varying embedded workloads. But reducing the VDD of the cache as aggressively as the VDD of the CPU logic is not straightforward, since standard 6T SRAMs cease to operate at lower VDDs. We implement a data and instruction filter cache, using logic cells located in the CPU VDD domain, to permit the level-1 (L1) cache to be reliably powered at a higher SRAM VDD. On top of eliminating many energy-wasting L1 cache accesses, the filter cache reduces the total number of executed cycles. Furthermore, the filter cache can be reconfigured as CPU VDD is reduced, to filter out an increasing proportion of cache accesses. We evaluate our approach using a 65-nm 1.2-V low-leakage CMOS process, with a minimal CPU and SRAM VDD of 0.4 and 0.95 V, respectively. Assuming 16kB+16kB L1 caches and 256B+256B filter caches, introducing the filter cache reduces the total cache access energy by 71% at 1.2 V and 87% at 0.4 V at an area overhead which is 13% of the L1 cache area.

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Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
in
2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
pages
4 pages
publisher
Institute of Electrical and Electronics Engineers Inc.
conference name
23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
external identifiers
  • scopus:85015325114
ISBN
9781509061136
DOI
10.1109/ICECS.2016.7841211
language
English
LU publication?
yes
id
f309dd40-3237-40d8-9a58-0734864ff23e
date added to LUP
2017-03-30 07:47:00
date last changed
2018-01-07 11:57:25
@inproceedings{f309dd40-3237-40d8-9a58-0734864ff23e,
  abstract     = {<p>Wide-VDD-range processors offer high energy efficiency for varying embedded workloads. But reducing the VDD of the cache as aggressively as the VDD of the CPU logic is not straightforward, since standard 6T SRAMs cease to operate at lower VDDs. We implement a data and instruction filter cache, using logic cells located in the CPU VDD domain, to permit the level-1 (L1) cache to be reliably powered at a higher SRAM VDD. On top of eliminating many energy-wasting L1 cache accesses, the filter cache reduces the total number of executed cycles. Furthermore, the filter cache can be reconfigured as CPU VDD is reduced, to filter out an increasing proportion of cache accesses. We evaluate our approach using a 65-nm 1.2-V low-leakage CMOS process, with a minimal CPU and SRAM VDD of 0.4 and 0.95 V, respectively. Assuming 16kB+16kB L1 caches and 256B+256B filter caches, introducing the filter cache reduces the total cache access energy by 71% at 1.2 V and 87% at 0.4 V at an area overhead which is 13% of the L1 cache area.</p>},
  author       = {Bardizbanyan, Alen and Andersson, Oskar and Rodrigues, Joachim and Larsson-Edefors, Per},
  booktitle    = {2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016},
  isbn         = {9781509061136},
  language     = {eng},
  month        = {02},
  pages        = {376--379},
  publisher    = {Institute of Electrical and Electronics Engineers Inc.},
  title        = {Logic filter cache for wide-VDD-range processors},
  url          = {http://dx.doi.org/10.1109/ICECS.2016.7841211},
  year         = {2017},
}