Analysis and design of an 1-20 GHz track and hold circuit
(2021) 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 In Proceedings - IEEE International Symposium on Circuits and Systems 2021-May.- Abstract
This work analyzes the nonlinear effects in the track and hold circuit applied in high-speed ADCs or RF sampling receiver (RX) front-ends. Non-ideal effects inside the main sampling NMOS switch are studied. Parasitic varactor and sampling on-resistance modulation effects are analyzed through frequency domain Volterra series and the EKV MOS transistor model. Polynomial curve fitting is applied showing that the on-resistance modulation dominates. Finally, a novel bootstrap circuit is proposed with a fast settling time and high bootstrap voltage in a 22 nm FD-SOI CMOS technology, with its settling time analyzed using the Elmore delay model.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/f342842e-e5e0-4afe-8c2f-d84d48994ee2
- author
- Chen, Peng LU ; Andersson, Stefan ; Gunnarsson, Sten E. and Sjöland, Henrik LU
- organization
- publishing date
- 2021
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- host publication
- 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
- series title
- Proceedings - IEEE International Symposium on Circuits and Systems
- volume
- 2021-May
- article number
- 9401599
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- conference name
- 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
- conference location
- Daegu, Korea, Republic of
- conference dates
- 2021-05-22 - 2021-05-28
- external identifiers
-
- scopus:85109030008
- ISSN
- 0271-4310
- ISBN
- 9781728192017
- DOI
- 10.1109/ISCAS51556.2021.9401599
- language
- English
- LU publication?
- yes
- id
- f342842e-e5e0-4afe-8c2f-d84d48994ee2
- date added to LUP
- 2021-08-13 14:37:50
- date last changed
- 2024-04-06 06:42:13
@inproceedings{f342842e-e5e0-4afe-8c2f-d84d48994ee2, abstract = {{<p>This work analyzes the nonlinear effects in the track and hold circuit applied in high-speed ADCs or RF sampling receiver (RX) front-ends. Non-ideal effects inside the main sampling NMOS switch are studied. Parasitic varactor and sampling on-resistance modulation effects are analyzed through frequency domain Volterra series and the EKV MOS transistor model. Polynomial curve fitting is applied showing that the on-resistance modulation dominates. Finally, a novel bootstrap circuit is proposed with a fast settling time and high bootstrap voltage in a 22 nm FD-SOI CMOS technology, with its settling time analyzed using the Elmore delay model.</p>}}, author = {{Chen, Peng and Andersson, Stefan and Gunnarsson, Sten E. and Sjöland, Henrik}}, booktitle = {{2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings}}, isbn = {{9781728192017}}, issn = {{0271-4310}}, language = {{eng}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{Proceedings - IEEE International Symposium on Circuits and Systems}}, title = {{Analysis and design of an 1-20 GHz track and hold circuit}}, url = {{http://dx.doi.org/10.1109/ISCAS51556.2021.9401599}}, doi = {{10.1109/ISCAS51556.2021.9401599}}, volume = {{2021-May}}, year = {{2021}}, }