Generating hardware and software for RISC-V cores generated with Rocket Chip generator
(2021) 34th IEEE International System-on-Chip Conference, SOCC 2021 In International System on Chip Conference 2021-September. p.89-94- Abstract
This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow description of an algorithm as input and generates a combination of hardware (in Chisel) and software (in C) that interacts with the hardware. The hardware can be integrated with RISC-V cores created by the Rocket Chip generator and the software can be executed on these cores.The generated hardware requires similar amount of resources as the hand-written hardware while achieving equal or higher clock rates. As expected, the accelerators perform the calculations faster than the general... (More)
This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow description of an algorithm as input and generates a combination of hardware (in Chisel) and software (in C) that interacts with the hardware. The hardware can be integrated with RISC-V cores created by the Rocket Chip generator and the software can be executed on these cores.The generated hardware requires similar amount of resources as the hand-written hardware while achieving equal or higher clock rates. As expected, the accelerators perform the calculations faster than the general purpose processor, 5 to 33x in our experiments. When these accelerators are integrated with the Rocket cores, they increase the performance by 25% and 260% in the two use-cases we investigate.
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- author
- Savas, Suleyman LU ; Bezati, Endri and Janneck, Jorn W. LU
- organization
- publishing date
- 2021
- type
- Chapter in Book/Report/Conference proceeding
- publication status
- published
- subject
- keywords
- accelerator, Chisel, dataflow, hardware/software co-design, RISC-V
- host publication
- Proceedings - 34th IEEE International System-on-Chip Conference, SOCC 2021
- series title
- International System on Chip Conference
- editor
- Qu, Gang ; Xiong, Jinjun ; Zhao, Danella ; Muthukumar, Venki ; Reza, Md Farhadur and Sridhar, Ramalingam
- volume
- 2021-September
- pages
- 6 pages
- publisher
- IEEE Computer Society
- conference name
- 34th IEEE International System-on-Chip Conference, SOCC 2021
- conference location
- Virtual, Online, United States
- conference dates
- 2021-09-14 - 2021-09-17
- external identifiers
-
- scopus:85127775912
- ISSN
- 2164-1706
- 2164-1676
- ISBN
- 9781665429313
- DOI
- 10.1109/SOCC52499.2021.9739411
- language
- English
- LU publication?
- yes
- id
- fef52398-2253-4087-8a1d-ca09ddca1a74
- date added to LUP
- 2022-06-14 13:31:08
- date last changed
- 2024-03-21 02:37:23
@inproceedings{fef52398-2253-4087-8a1d-ca09ddca1a74,
abstract = {{<p>This paper presents the hardware/software generation backend of a code generation framework. The backend aims at synthesizing complete systems based on RISC-V cores with accelerators from a single-language description. The framework takes the dataflow description of an algorithm as input and generates a combination of hardware (in Chisel) and software (in C) that interacts with the hardware. The hardware can be integrated with RISC-V cores created by the Rocket Chip generator and the software can be executed on these cores.The generated hardware requires similar amount of resources as the hand-written hardware while achieving equal or higher clock rates. As expected, the accelerators perform the calculations faster than the general purpose processor, 5 to 33x in our experiments. When these accelerators are integrated with the Rocket cores, they increase the performance by 25% and 260% in the two use-cases we investigate. </p>}},
author = {{Savas, Suleyman and Bezati, Endri and Janneck, Jorn W.}},
booktitle = {{Proceedings - 34th IEEE International System-on-Chip Conference, SOCC 2021}},
editor = {{Qu, Gang and Xiong, Jinjun and Zhao, Danella and Muthukumar, Venki and Reza, Md Farhadur and Sridhar, Ramalingam}},
isbn = {{9781665429313}},
issn = {{2164-1706}},
keywords = {{accelerator; Chisel; dataflow; hardware/software co-design; RISC-V}},
language = {{eng}},
pages = {{89--94}},
publisher = {{IEEE Computer Society}},
series = {{International System on Chip Conference}},
title = {{Generating hardware and software for RISC-V cores generated with Rocket Chip generator}},
url = {{http://dx.doi.org/10.1109/SOCC52499.2021.9739411}},
doi = {{10.1109/SOCC52499.2021.9739411}},
volume = {{2021-September}},
year = {{2021}},
}