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- 2011
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Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
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Mark
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
2011) IEEE European Test Symposium (ETS), 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Design Automation for IEEE P1687
2011) Design, Automation and Test in Europe (DATE 2011),(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
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Mark
Optimizing Fault Tolerance for Multi-Processor System-on-Chip
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
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Mark
A Distributed Architecture to Check Global Properties for Post-Silicon Debug
2010) IEEE European Test Symposium (ETS'10), 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Test Time Analysis for IEEE P1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Efficient Embedding of Deterministic Test Data
2010) 19th IEEE Asian Test Symposium (ATS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
2010) The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10)Chicago, Illinois, USA, June 28-July 1, 2010. p.121-130(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding