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- 2000
-
Mark
A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 1999
-
Mark
Power Reduction in Custom CMOS Digital Filter Structures
(
- Contribution to journal › Article
-
Mark
High bandwidth iterative decoding in a fading environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Design of a High Throughput Serial Concatenated Convolution Decoder
1999) NORCHIP Conference, 1999(
- Contribution to conference › Paper, not in proceeding
- 1997
-
Mark
A Custom Digital Intermediate Frequency Filter for the American Mobile Telephone System
(
- Contribution to journal › Article
-
Mark
Low Power Optimization of Bit-Serial Digital Filters
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Low Power Lattice Wave Digital Bit-Serial Filters
1997) 5th International Conference VLSI and CAD (ICVC’97)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Coefficient Optimization for Low Power Digital Filters
1997) NORCHIP Conference, 1997(
- Contribution to conference › Paper, not in proceeding
-
Mark
Implementation of Low Power Lattice Wave Digital Filters
1997) European Microelectronics Application Conference 1997 (EMAC’97)(
- Contribution to conference › Paper, not in proceeding
- 1996
-
Mark
A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's
(
- Contribution to journal › Article