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- 2008
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Mark
VHDL vs. Bluespec System Verilog: A case study on a Java embedded architecture
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Reporting experiments in software engineering
2008) p.201-228(
- Chapter in Book/Report/Conference proceeding › Book chapter
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Mark
Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems
2008) p.15-29(
- Chapter in Book/Report/Conference proceeding › Book chapter
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Mark
The effect of syntactic representation on semantic role labeling
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
It takes two to Tango!
2008) LTHs 5:e Pedagogiska Inspirationskonferens, 2008(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
UML and SystemC - Comparison and Mapping Rules for Automatic Code Generation
2008) FDL 2007: Forum on specification & Design Languages In Lecture Notes in Electrical Engineering 10. p.199-209(
- Chapter in Book/Report/Conference proceeding › Book chapter
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Mark
Empirical evaluations of regression test selection techniques: a systematic review
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Conditional Partial Plans for Rational Situated Agents Capable of Deductive Reasoning and Inductive Learning
2008)(
- Thesis › Doctoral thesis (monograph)
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Mark
A Framework for Simulation of Requirements Engineering Processes
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Dependency-based semantic role labeling of PropBank
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding