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- 2017
-
Mark
Digital Phase Locked Loops for Radio Frequency Synthesis
2017)(
- Thesis › Doctoral thesis (monograph)
- 2016
-
Mark
A 1.5 V 28 GHz beam steering SiGe PLL for an 81-86 GHz E-band transmitter
(
- Contribution to journal › Article
- 2005
-
Mark
Delay-locked loop and its applications
(
- Contribution to journal › Article
- 2004
-
Mark
Distributed Clocking and Clock Generation in Digital CMOS SoC ASICs
2004)(
- Thesis › Doctoral thesis (compilation)