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Low-Latency Resampling Architectures for Particle Filters on FPGA

Liu, Xingyu LU (2026) EITM02 20261
Department of Electrical and Information Technology
Abstract
As wireless communication systems evolve toward 6G and joint communication
and sensing paradigms, emerging applications impose stringent low-latency constraints
on target tracking systems. Within the hardware implementation of particle
filters, the traditional systematic resampling algorithm suffers from global
data dependencies and sequential memory accesses, creating a fundamental performance
bottleneck.
To address this latency issue, this report designs, implements, and evaluates
two distinct resampling architectures on an FPGA platform.
The first design is an optimized sequential architecture that utilizes pre-fetching
logic to effectively mask the inherent read latency of the on-chip memory.
To completely break the... (More)
As wireless communication systems evolve toward 6G and joint communication
and sensing paradigms, emerging applications impose stringent low-latency constraints
on target tracking systems. Within the hardware implementation of particle
filters, the traditional systematic resampling algorithm suffers from global
data dependencies and sequential memory accesses, creating a fundamental performance
bottleneck.
To address this latency issue, this report designs, implements, and evaluates
two distinct resampling architectures on an FPGA platform.
The first design is an optimized sequential architecture that utilizes pre-fetching
logic to effectively mask the inherent read latency of the on-chip memory.
To completely break the sequential bottleneck, the second design introduces a
parallel architecture based on the Metropolis-Hastings algorithm. By employing
an array of independent processing elements and a decentralized memory topology,
combining private working memories with dual-port shared read-only memories,
this architecture eliminates global data dependency and avoids the routing congestion
and stall penalties associated with traditional crossbar switches.
Hardware results at a 100 MHz clock frequency demonstrate that the optimized
sequential architecture achieves an execution time of 81.98 μs. Furthermore, the
parallel architecture utilizing 16 PEs when dynamically downscaled to 4 iterations
reduces the execution latency to 10.49 μs delivering a 15.6 times speedup compared
to the standard baseline.
While the parallel approach consumes more Block RAM and digital signal
processing resources and exhibits a bounded statistical degradation, this trade-off
provides a mathematically sound and scalable hardware solution to meet the real
time demands of next generation applications. (Less)
Popular Abstract
This thesis tackles a critical bottleneck in future 6G, robotics, and AR systems: the need for zero-delay object tracking. Engineers achieve this tracking via Particle Filters, which run thousands of particles to guess an object's position. However, the "resampling" phase, which duplicates accurate guesses and discards poor ones, and this causes a massive digital traffic jam. Traditional hardware forces all particles to wait in a single line to calculate a global total before making a move. This project completely redesigns the hardware layout inside an FPGA microchip to smash this bottleneck, implementing and evaluating two novel architectures.
Please use this url to cite or link to this publication:
author
Liu, Xingyu LU
supervisor
organization
course
EITM02 20261
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH-EIT 2026-1123
language
English
id
9230867
date added to LUP
2026-06-08 16:06:08
date last changed
2026-06-08 16:06:08
@misc{9230867,
  abstract     = {{As wireless communication systems evolve toward 6G and joint communication
and sensing paradigms, emerging applications impose stringent low-latency constraints
on target tracking systems. Within the hardware implementation of particle
filters, the traditional systematic resampling algorithm suffers from global
data dependencies and sequential memory accesses, creating a fundamental performance
bottleneck.
To address this latency issue, this report designs, implements, and evaluates
two distinct resampling architectures on an FPGA platform.
The first design is an optimized sequential architecture that utilizes pre-fetching
logic to effectively mask the inherent read latency of the on-chip memory.
To completely break the sequential bottleneck, the second design introduces a
parallel architecture based on the Metropolis-Hastings algorithm. By employing
an array of independent processing elements and a decentralized memory topology,
combining private working memories with dual-port shared read-only memories,
this architecture eliminates global data dependency and avoids the routing congestion
and stall penalties associated with traditional crossbar switches.
Hardware results at a 100 MHz clock frequency demonstrate that the optimized
sequential architecture achieves an execution time of 81.98 μs. Furthermore, the
parallel architecture utilizing 16 PEs when dynamically downscaled to 4 iterations
reduces the execution latency to 10.49 μs delivering a 15.6 times speedup compared
to the standard baseline.
While the parallel approach consumes more Block RAM and digital signal
processing resources and exhibits a bounded statistical degradation, this trade-off
provides a mathematically sound and scalable hardware solution to meet the real
time demands of next generation applications.}},
  author       = {{Liu, Xingyu}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Low-Latency Resampling Architectures for Particle Filters on FPGA}},
  year         = {{2026}},
}