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On-Chip Runtime Frequency Feedback Closed-Loop Scheme for Low-Power Management

Zhan, Tong LU and Sun, Jianpeng LU (2026) EITM02 20261
Department of Electrical and Information Technology
Abstract
This thesis studies a runtime frequency feedback method for low-power digital systems. Conventional low-power designs usually reserve extra voltage and timing margins to ensure stable chip operation under process, voltage, temperature, and aging variations. However, fixed margins can also lead to unnecessary power consumption. To address this problem, this thesis proposes and implements a Runtime Frequency Feedback system. The system observes the current silicon speed through a VCRO-based frequency sensing path and provides this information to later low-power feedback control logic. The thesis covers behavioral modeling, system design, RTL circuit implementation, and functional verification. The results show that the proposed design can... (More)
This thesis studies a runtime frequency feedback method for low-power digital systems. Conventional low-power designs usually reserve extra voltage and timing margins to ensure stable chip operation under process, voltage, temperature, and aging variations. However, fixed margins can also lead to unnecessary power consumption. To address this problem, this thesis proposes and implements a Runtime Frequency Feedback system. The system observes the current silicon speed through a VCRO-based frequency sensing path and provides this information to later low-power feedback control logic. The thesis covers behavioral modeling, system design, RTL circuit implementation, and functional verification. The results show that the proposed design can provide a practical hardware basis for sensing runtime timing capability, reducing conservative design margins, and supporting more adaptive low-power management. (Less)
Popular Abstract
Chips are used in phones, computers, cameras, cars, and many smart devices. People expect chips to be fast, stable, and energy efficient. To prevent errors caused by temperature changes, manufacturing differences, or aging, engineers usually keep a large safety margin in chip design. This is similar to keeping a long safety distance when driving. It is safer, but it can also waste energy when the margin is larger than needed.

This thesis asks whether a chip can observe its own condition while it is running, instead of always working under the most conservative assumption. To do this, the thesis designs a Runtime Frequency Feedback system. In simple terms, it works like a small speed sensor inside the chip. It helps the system estimate... (More)
Chips are used in phones, computers, cameras, cars, and many smart devices. People expect chips to be fast, stable, and energy efficient. To prevent errors caused by temperature changes, manufacturing differences, or aging, engineers usually keep a large safety margin in chip design. This is similar to keeping a long safety distance when driving. It is safer, but it can also waste energy when the margin is larger than needed.

This thesis asks whether a chip can observe its own condition while it is running, instead of always working under the most conservative assumption. To do this, the thesis designs a Runtime Frequency Feedback system. In simple terms, it works like a small speed sensor inside the chip. It helps the system estimate how fast the chip can currently operate. If the chip is in a good condition, there may be room to reduce unnecessary power use. If the condition becomes worse, the system can detect the risk earlier.

This thesis includes modeling, hardware design, and simulation-based verification. The work studies how to calibrate this “speed sensor,” how to measure its output, and how to provide the measured result to later low-power control logic. Overall, this thesis aims to provide a practical hardware basis for smarter and more adaptive low-power management in future chip systems. (Less)
Please use this url to cite or link to this publication:
author
Zhan, Tong LU and Sun, Jianpeng LU
supervisor
organization
course
EITM02 20261
year
type
H2 - Master's Degree (Two Years)
subject
keywords
Runtime Frequency Feedback, Low-Power Management, VCRO, Frequency Sensing, RTL Design, Functional Verification, Calibration, Digital Integrated Circuits
report number
LU/LTH-EIT 2026-1125
language
English
id
9232116
date added to LUP
2026-06-08 16:16:52
date last changed
2026-06-08 16:16:52
@misc{9232116,
  abstract     = {{This thesis studies a runtime frequency feedback method for low-power digital systems. Conventional low-power designs usually reserve extra voltage and timing margins to ensure stable chip operation under process, voltage, temperature, and aging variations. However, fixed margins can also lead to unnecessary power consumption. To address this problem, this thesis proposes and implements a Runtime Frequency Feedback system. The system observes the current silicon speed through a VCRO-based frequency sensing path and provides this information to later low-power feedback control logic. The thesis covers behavioral modeling, system design, RTL circuit implementation, and functional verification. The results show that the proposed design can provide a practical hardware basis for sensing runtime timing capability, reducing conservative design margins, and supporting more adaptive low-power management.}},
  author       = {{Zhan, Tong and Sun, Jianpeng}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{On-Chip Runtime Frequency Feedback Closed-Loop Scheme for Low-Power Management}},
  year         = {{2026}},
}