Thermal Aware Floorplan Techniques for ASICs

Abstract

As transistors get smaller and smaller, the power density of an integrated circuit increases and thus the temperature increases. In an application specific integrated circuit (ASIC) the layout is tailor-made for each design, so the thermal signature of each component can be taken into account during the floorplanning process. Although approaches for thermal aware floorplanning exists, they aren't generalizable to new floorplans and can't handle hierarchical structures adequately. In this thesis we present a method to do thermal-aware compact floorplanning that is also generalizable through the use of reinforcement learning. We present a novel way to do hierachical divisions within the ASIC to improve connectivity, a new fast analytical thermal simulator and also utilize simulated annealing with reinforcement learning (SARL) in VLSI floorplanning for the first time. Our results are very successful demonstrating an automated flow for generating thermal aware floorplans.

Abstract (Swedish)

I takt med att transistorerna blir mindre och mindre ökar effekttätheten i en integrerad krets, vilket leder till att temperaturen stiger. I en applikationsspecifik integrerad krets (ASIC) skräddarsys layouten för varje enskild konstruktion, vilket gör att varje komponents termiska signatur kan beaktas redan under planeringsprocessen. Det finns existerande lösningar för detta problem, men de kan inte generalisera till nya chip eller hanterar hierakiska strukturer. I denna avhandling presenterar vi en metod för termiskt medveten chip design som dessutom kan generaliseras genom användning av reinforcement learning. Vi presenterar ett nytt sätt att göra hierarkiska uppdelningar inom en ASIC för att förbättra konnektiviteten, har utvecklat en ny snabb analytisk termisk simulator och använder även reinforcement learning med simulerad annealing (SARL) tillsammans för första gången. Våra resultat är mycket framgångsrika och demonstrerar en automatiserad metod för att designa ASIC med temperatur i åtanke.

Popular Abstract

Over the past few decades decades, transistors, the smallest component on a chip, have been halving in size every 2 years. This decrease in size causes more current to be focused in a smaller area and thus the temperature increases. Higher temperatures have a significant impact on the performance of these chips, often called integrated circuits, leading to higher power consumption and reducing the lifespan of the circuit. It is therefore imperative to reduce the temperature of an integrated circuit, especially in situations where active cooling isn't available.

To suit user defined purposes, Application-Specific Integrated Circuits (ASICs) are designed with very specified functionalities and require tailor-made layouts for each application. Each ASIC can be broken down hierarchically into smaller blocks (in our case rectangles), where each block realizes a specific function. An ASIC layout is often referred to as a floorplan, and floorplanning is the process of choosing the best placement of blocks on a die given certain costs and constraints. Traditional floorplanning methods have primarily focused on increasing area utilization and decreasing wirelength, however as transistors have gotten smaller, the higher temperatures necessitate for it to also be optimized for.

In our thesis we developed an automated method for thermal-aware ASIC floorplanning that takes area, wirelength and temperature into account. Our algorithm first analyzes the connectivity between blocks in the floorplan and clusters them into groups. These groups are divided into larger zones, with connection cells between them to wire the floorplan together. Once the groups and zones have been set, a random floorplan is created using a representation called CB trees. This representation is iteratively perturbed such as moving a block, rotating a block or changing the aspect ratio. We use a simulated annealing acceptance criteria such that if a perturbation improves the overall cost then it is kept, and otherwise it is kept with a diminishing probability over the number of iterations. Commonly, simulated annealing is applied using random moves, however we designed an AI algorithm using a method called reinforcement learning to that has learned to make moves smartly from other ASICs. Once an approximate solution has been found, the solution goes through a refinement step to modify the aspect ratios of the blocks and flips in order to find the absolute best solution. For all of this to work we also had to develop our own thermal simulation software, and make it fast in order to run many iterations. Our final results have been very successful demonstrating an automated flow for generating thermal aware floorplans.

• author: Biswas, Soumya and Franzén, Albin
• supervisor: Victor Åberg
• organization: Department of Electrical and Information Technology
• course: EITM02 20261
• year: 2026
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Thermal-Aware Floorplanning, Reinforcement Learning, ASIC Design, Electronic Design Automation, Heat Dissipation, Placement Optimization, Physical Design
• report number: LU/LTH-EIT 2026-1145
• language: English
• additional info: This Master thesis project was done in collaboration with Ericsson AB, Lund.
• id: 9235207
• date added to LUP: 2026-06-15 13:27:09
• date last changed: 2026-06-15 13:27:09