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Functional Verification of SPI Controller using UVM

Yu, Yanqian LU (2026) EITM02 20261
Department of Electrical and Information Technology
Abstract (Swedish)
Radio Frequency Integrated Circuits (RFICs) play a crucial role in modern wireless communica-
tion systems. However, they can achieve high performance only when their internal registers are
dynamically and precisely configured. To maintain reliable control while operating in complex
multi-antenna environments, several interface techniques have been developed, among which the
Serial Peripheral Interface (SPI) control module is one of the most critical bridges for translating
system bus requests into SPI transactions.
In this thesis, we designed and analyzed a comprehensive Universal Verification Methodology
(UVM) environment for an SPI_CTRL module consisting of a dual block random access
memory(BRAM) architecture and eight... (More)
Radio Frequency Integrated Circuits (RFICs) play a crucial role in modern wireless communica-
tion systems. However, they can achieve high performance only when their internal registers are
dynamically and precisely configured. To maintain reliable control while operating in complex
multi-antenna environments, several interface techniques have been developed, among which the
Serial Peripheral Interface (SPI) control module is one of the most critical bridges for translating
system bus requests into SPI transactions.
In this thesis, we designed and analyzed a comprehensive Universal Verification Methodology
(UVM) environment for an SPI_CTRL module consisting of a dual block random access
memory(BRAM) architecture and eight independent SPI channels. This work began with
the development of a verification architecture to ensure the testbench effectively stimulates
the design’s internal request FIFO and state machines. Based on this design, we evaluated its
behavior across various clock domain crossing (CDC) conditions and continuous read/write
requests, gaining insight into its scheduling performance and functional completeness.
This work evaluates the impact of concurrent high-speed AXI4-Lite transactions on the
SPI_CTRL’s stability. With the increasing demand for high integration and flexibility in wireless
systems, handling massive parallel data translation has become an essential requirement. However,
dynamic operating conditions and varying request timings introduce complex corner cases that
challenge the adaptability and reliability of traditional directed testing methods.
This thesis analyzes the functional coverage of the SPI_CTRL design under varying request
traffic and checks if all logical anomalies and timing violations can be eliminated by employing
the UVM framework. (Less)
Please use this url to cite or link to this publication:
author
Yu, Yanqian LU
supervisor
organization
course
EITM02 20261
year
type
H2 - Master's Degree (Two Years)
subject
keywords
Universal Verification Methodology (UVM), Serial Peripheral Interface (SPI), Ad- vanced eXtensible Interface (AXI), Functional Verification, Constrained-Random Testing, Dual-BRAM Architecture
report number
LU/LTH-EIT 2026-1115
language
English
id
9235496
date added to LUP
2026-06-15 10:41:38
date last changed
2026-06-15 10:41:38
@misc{9235496,
  abstract     = {{Radio Frequency Integrated Circuits (RFICs) play a crucial role in modern wireless communica-
tion systems. However, they can achieve high performance only when their internal registers are
dynamically and precisely configured. To maintain reliable control while operating in complex
multi-antenna environments, several interface techniques have been developed, among which the
Serial Peripheral Interface (SPI) control module is one of the most critical bridges for translating
system bus requests into SPI transactions.
 In this thesis, we designed and analyzed a comprehensive Universal Verification Methodology
(UVM) environment for an SPI_CTRL module consisting of a dual block random access
memory(BRAM) architecture and eight independent SPI channels. This work began with
the development of a verification architecture to ensure the testbench effectively stimulates
the design’s internal request FIFO and state machines. Based on this design, we evaluated its
behavior across various clock domain crossing (CDC) conditions and continuous read/write
requests, gaining insight into its scheduling performance and functional completeness.
 This work evaluates the impact of concurrent high-speed AXI4-Lite transactions on the
SPI_CTRL’s stability. With the increasing demand for high integration and flexibility in wireless
systems, handling massive parallel data translation has become an essential requirement. However,
dynamic operating conditions and varying request timings introduce complex corner cases that
challenge the adaptability and reliability of traditional directed testing methods.
 This thesis analyzes the functional coverage of the SPI_CTRL design under varying request
traffic and checks if all logical anomalies and timing violations can be eliminated by employing
the UVM framework.}},
  author       = {{Yu, Yanqian}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Functional Verification of SPI Controller using UVM}},
  year         = {{2026}},
}