Pipeline ADC PN-Dither LMS Background Calibration: FPGA and ASIC Digital Back-End Implementation

Abstract

This thesis presents a complete digital back-end implementation of a PN-dither
least-mean-squares (LMS) background calibration scheme for a 12-bit, 500 MS/s
pipeline analog-to-digital converter (ADC). The target converter, designed by a
parallel analog project, comprises four 3-bit stages and a 4-bit final flash stage; its
actual inter-stage gains depart substantially from their nominal values, reducing
the effective number of bits (ENOB) of the uncalibrated output to 4.19 bits. The
back-end injects a small pseudo-noise dither at the residue path of each calibrated
stage and uses a one-tap LMS update to track the gain errors in real time. A
division-free reconstruction datapath, obtained by algebraic rearrangement of the
standard reconstruction equation, recovers the calibrated output using only multiplications
and additions. A parametric study of the gain-accumulator bit width
identifies a stochastic-quantisation regime that informs the choice of a 24-bit accumulator
(S3.20 format), trading 0.26 bits of ENOB for a 53% reduction in look-up
table count relative to a full-precision reference.
The same Verilog source has been carried through both an FPGA verification
flow and an ASIC physical-implementation flow. On a Xilinx Artix-7 XC7A100T
the design closes timing at 58.8MHz with 721 LUTs, 577 flip-flops, 11 DSP48
blocks, and 113mW of total power. On a 65 nm CMOS process the placed-androuted
layout occupies 0.031mm2 and dissipates 2.07mW under default activity—
a factor of 55× lower than the FPGA target. The achieved steady-state ENOB
of 7.20 bits exceeds the project objective of 7 bits and demonstrates that a heavily
resource-optimised digital calibration back-end can match the spectral performance
of a full-precision baseline in production-silicon form.

Popular Abstract

Modern wireless networks, medical imaging devices, and self-driving cars all rely
on a small but critical electronic component called an analog-to-digital converter
(ADC), which turns continuously varying signals into the streams of numbers that
a computer can process. Like a ruler whose markings are slightly bent, real ADCs
are never perfect: imperfections in the analog circuitry, drift with temperature,
and aging cause some bits of the output to be wrong. The converter studied in
this thesis has a 12-bit hardware design, but with the uncorrected analog errors it
delivers an effective resolution of only about four bits.
This thesis builds a digital self-correction circuit that sits alongside the analog
ADC and quietly fixes its imperfections while the converter is running. A tiny
known random nudge is added into the analog signal; by watching where that
nudge ends up in the digital output, the circuit deduces how large each analog error
is and updates a small set of correction numbers in the background—using a longestablished
adaptive-filter algorithm that also powers noise-cancelling headphones.
The same hardware description has been implemented both on a reconfigurable
prototyping chip (FPGA) and as a custom integrated circuit in a mainstream
65nm silicon process. The custom-silicon version occupies an area about the size
of a sand grain, dissipates only two milliwatts of power—more than fifty times
less than the FPGA prototype—and recovers more than seven bits of effective
resolution from a converter that, uncorrected, manages only four.

• author: Wang, Xingyu
• supervisor: Baktash Behmanesh
• organization: Department of Electrical and Information Technology
• course: EITM02 20261
• year: 2026
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Pipeline ADC, Background calibration, LMS algorithm, Digital calibration, Analog-to-digital converter (ADC), Mixed-signal integrated circuits
• report number: LU/LTH-EIT 2026-1154
• language: English
• id: 9239260
• date added to LUP: 2026-06-16 13:43:32
• date last changed: 2026-06-16 13:43:32