Multi-Phase Clock Generation for Programmable Broadband Delay Circuits
(2026) EITM02 20261Department of Electrical and Information Technology
- Abstract
- Many circuits in integrated-circuit design require a time-shifted or multi-phase clock. In time-interleaved ADCs, multiple phases enable a higher effective aggregate sampling rate without increasing the individual clock rate. In contrast, in SerDes links, bit throughput increases while keeping each lane at a lower base clock. In 5G and 6G wireless equipment, multiple phases can be used to drive a true time delay (TTD) block, enabling programmable broadband delays for applications ranging from beamforming to power-amplifier predistortion. This work targets the latter: a bank of phases at a fixed frequency clocks the sample-and-hold taps of a TTD network, where the selected phase sets the delay applied to the sampled signal. The achievable... (More)
- Many circuits in integrated-circuit design require a time-shifted or multi-phase clock. In time-interleaved ADCs, multiple phases enable a higher effective aggregate sampling rate without increasing the individual clock rate. In contrast, in SerDes links, bit throughput increases while keeping each lane at a lower base clock. In 5G and 6G wireless equipment, multiple phases can be used to drive a true time delay (TTD) block, enabling programmable broadband delays for applications ranging from beamforming to power-amplifier predistortion. This work targets the latter: a bank of phases at a fixed frequency clocks the sample-and-hold taps of a TTD network, where the selected phase sets the delay applied to the sampled signal. The achievable delay range and resolution are therefore set directly by the number of phases and their spacing, motivating a generator that produces many accurately spaced phases at RF. This thesis presents a duty-cycle-controlled multi-phase clock generator that achieves 90 fs cycle-to-cycle jitter at 5.64 mW total system power. (Less)
- Popular Abstract
- Imagine you were at a game contest with 4 of your friends. To make it fun, the rules
are weird.
• Each of your friends is on a swing and needs you to push them.
• Each time you push, a buzzer makes a specific sound.
• Each time a friend gets 5 pushes, a different buzzer sounds.
• No swing must stay still for more than 20 seconds. So you run around and push
each friend 5 times each. Then start over.
Now think about it. Your buzzer sounds once every second, but each of your friends’ buzzers sounds once every 20 seconds. Congratulations, you’ve just created 5 different clocks. You are the main clock, and each of your friends is a clock that is 4 times slower than yours. Even more, each of your friends’ clocks are spaced in time.... (More) - Imagine you were at a game contest with 4 of your friends. To make it fun, the rules
are weird.
• Each of your friends is on a swing and needs you to push them.
• Each time you push, a buzzer makes a specific sound.
• Each time a friend gets 5 pushes, a different buzzer sounds.
• No swing must stay still for more than 20 seconds. So you run around and push
each friend 5 times each. Then start over.
Now think about it. Your buzzer sounds once every second, but each of your friends’ buzzers sounds once every 20 seconds. Congratulations, you’ve just created 5 different clocks. You are the main clock, and each of your friends is a clock that is 4 times slower than yours. Even more, each of your friends’ clocks are spaced in time. They have the same frequency, but they are operating spaced every 5 "ticks" of your clock. If you could take this game further with more people, someone in another part of the game could do something every time they hear a specific buzzer. And since your friends’ buzzers are all spaced in time, those people would be doing things at the same frequency just at different times. This is called Multi-Phase Clocks. In electronics, these are an important building block used in various circuits. The basis of this thesis is the creation of such clocks and their accuracy when produced. Our fastest clock operates at 16GHz, that’s you pushing a swing once every 62.5 ps or 16 billion times every second! (Less)
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/student-papers/record/9240613
- author
- James, Armon Horace LU
- supervisor
- organization
- course
- EITM02 20261
- year
- 2026
- type
- H2 - Master's Degree (Two Years)
- subject
- keywords
- Clock generation, multi-phase clock, analogue predistortion, duty-cycle control, true time delay (TTD), flip-flop, ring counter
- report number
- LU/LTH-EIT 2026-1171
- language
- English
- id
- 9240613
- date added to LUP
- 2026-06-17 14:25:57
- date last changed
- 2026-06-17 14:25:57
@misc{9240613,
abstract = {{Many circuits in integrated-circuit design require a time-shifted or multi-phase clock. In time-interleaved ADCs, multiple phases enable a higher effective aggregate sampling rate without increasing the individual clock rate. In contrast, in SerDes links, bit throughput increases while keeping each lane at a lower base clock. In 5G and 6G wireless equipment, multiple phases can be used to drive a true time delay (TTD) block, enabling programmable broadband delays for applications ranging from beamforming to power-amplifier predistortion. This work targets the latter: a bank of phases at a fixed frequency clocks the sample-and-hold taps of a TTD network, where the selected phase sets the delay applied to the sampled signal. The achievable delay range and resolution are therefore set directly by the number of phases and their spacing, motivating a generator that produces many accurately spaced phases at RF. This thesis presents a duty-cycle-controlled multi-phase clock generator that achieves 90 fs cycle-to-cycle jitter at 5.64 mW total system power.}},
author = {{James, Armon Horace}},
language = {{eng}},
note = {{Student Paper}},
title = {{Multi-Phase Clock Generation for Programmable Broadband Delay Circuits}},
year = {{2026}},
}