High Throughput Matrix Inversion Implementation for Distributed MIMO Testbed on ZCU102

Abstract

Matrix inversion is a computationally demanding operation in the distributed multiple-input multiple-output (D-MIMO) systems. In zero-forcing detection, channel information from multiple access points is combined into a Gram matrix whose inverse is required to suppress multi-user interference. Computing this inverse accurately under strict latency and throughput constraints is challenging on an FPGA, where both arithmetic and memory resources are limited.

This thesis presents a high-throughput 32 × 32 matrix inversion implementation for the D-MIMO testbed at Lund University. Instead of directly inverting the full Gram matrix, a structured preconditioner is first constructed from its tri-diagonal region. To reduce the hardware cost of the preconditioner inversion, the full matrix is approximated by diagonal blocks. Each block is inverted using Cuppen’s divide-and-conquer eigenvalue decomposition after a complex-to-real similarity transformation. The resulting block-diagonal inverse is then refined using the original 32 × 32 Gram matrix through a factorized Neumann Series (NS).

The accelerator targets the AMD ZCU102 FPGA platform. The divide-and-conquer path is time-multiplexed eight-fold, while four secular solvers operate in parallel. The 32 × 32 NS engine uses two physical 16 × 16 processing element arrays that are reused across four logical matrix tiles. Banked memories, local ping-pong storage, and concurrent execution between the two arrays are used to reduce data movement and expose parallelism without instantiating a full 32 × 32 matrix-multiplication array.

Post-implementation utilization report illustrates the high hardware cost of the algorithm. The measured end-to-end computation latency is 2205 clock cycles for a Gram matrix inversion with three NS iterations, and a throughput of 1113 clock cycles per Gram inversion. RTL simulation over 600 distinct Gram matrices gives an average mean-square error of 4.35 × 10^−3 and a 64-QAM bit error rate of approximately 1.22 × 10^−2. The results confirm that the proposed implementation satisfies the throughput requirement of 1329 clock cycles per inversion while maintaining reasonable accuracy, thereby validating the practical viability of the design.

Popular Abstract

Imagine a crowded train station where many people speak at once. A wireless receiver faces a similar problem: it must separate several users’ signals before the
next batch of data arrives.

Modern wireless systems can use many antenna panels placed at different locations and make them work together. This approach, called distributed MIMO, can improve coverage and reliability. However, combining many users also creates a difficult calculation inside the receiver. For the D-MIMO testbed in EIT Department, one important step involves repeatedly processing a 32 by 32 table of numbers that describes how the users’ radio signals interact. The receiver must
effectively “unmix” these signals, and matrix inversion is a key part of that task.

Matrix inversion is easy to write as mathematics, but expensive to perform directly in hardware. Calculating everything in parallel would require more computing units than is practical on the target chip. Using fewer units saves hardware, but risks becoming too slow. The challenge is therefore to find a useful balance between speed, accuracy, and available resources.

This thesis develops a standalone matrix-inversion accelerator on an FPGA that can perform inverse operations continuously. Rather than solving the full problem in one step, the design first creates a good starting estimate from eight smaller pieces. It then uses the complete 32 × 32 matrix to correct said estimate. This is similar to solving several small parts of a puzzle first and then using the full picture to fix the remaining errors. The hardware also reuses the same modular units for different stages of the compute and allows independent stages to work simultaneously.

• author: Wang, Wei-Tang and Liu, Yifan
• supervisor: Sijia Cheng
• organization: Department of Electrical and Information Technology
• course: EITM02 20261
• year: 2026
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: 6G, Wireless Communication, D-MIMO, Massive MIMO, MIMO, Gram Matrix, Matrix Inversion, Neumann Series, Processing Element Array, Cuppen's Method, Divide and Conquer, Eigenvalue Decomposition, FPGA
• report number: LU/LTH-EIT 2026-1186
• language: English
• id: 9250302
• date added to LUP: 2026-09-23 10:57:57
• date last changed: 2026-10-26 08:19:54