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LUND UNIVERSITY LIBRARIES

Address Generation Unit (AGU) for a Custom DSP Core

Kong, Xiaoling LU (2026) EITM02 20261
Department of Electrical and Information Technology
Abstract
Highly efficient memory access and complex address computation are critical bottlenecks in modern Digital Signal Processors (DSPs). In conventional architectures, software-based address manipulation brings severe clock cycle penalties and register file pressure. Given that many typical workloads on DSP have highly regular data access patterns, this thesis presents a custom Address Generation Unit (AGU) tailored for a proprietary DSP developed by Silicon Integrated to address this challenge.
The proposed AGU accelerates execution by entirely offloading complex address calculations from the main datapath. It introduces advanced addressing capabilities, including post-modification, modulo, bit-reversal, and multi-dimensional addressing. To... (More)
Highly efficient memory access and complex address computation are critical bottlenecks in modern Digital Signal Processors (DSPs). In conventional architectures, software-based address manipulation brings severe clock cycle penalties and register file pressure. Given that many typical workloads on DSP have highly regular data access patterns, this thesis presents a custom Address Generation Unit (AGU) tailored for a proprietary DSP developed by Silicon Integrated to address this challenge.
The proposed AGU accelerates execution by entirely offloading complex address calculations from the main datapath. It introduces advanced addressing capabilities, including post-modification, modulo, bit-reversal, and multi-dimensional addressing. To strike an optimal balance between physical area overhead and operational flexibility, the first three addressing modes share unified hardware modules, while matrix calculation utilizes an independent dedicated module. Furthermore, the system's memory architecture and Instruction Set Architectures (ISA) is correspondingly refactored to support seamless integration.
The architectural performance was evaluated using four typical DSP benchmarks: FFT, FIR, IIR, and Matrix Multiplication. The integration of the AGU achieved at least a 50% reduction in execution clock cycles across all workloads, accompanied by substantial code size compression ranging from 10.5% to 46.2%. The physical hardware overhead was evaluated via pre-layout logic synthesis using the TowerJazz 65nm technology node. Although the improved architecture incurs a modest area increase of approximately 10.3% and a total power increase of 16.0%, the drastic reduction in execution time results in a significant decrease in the overall energy consumption per task. Ultimately, this work demonstrates a highly successful architectural enhancement, proving that the proposed AGU delivers a highly favorable energy-efficient DSP acceleration. (Less)
Please use this url to cite or link to this publication:
author
Kong, Xiaoling LU
supervisor
organization
course
EITM02 20261
year
type
H2 - Master's Degree (Two Years)
subject
report number
LU/LTH EIT-2026
language
English
id
9250869
date added to LUP
2026-09-24 13:38:55
date last changed
2026-09-24 13:38:55
@misc{9250869,
  abstract     = {{Highly efficient memory access and complex address computation are critical bottlenecks in modern Digital Signal Processors (DSPs). In conventional architectures, software-based address manipulation brings severe clock cycle penalties and register file pressure. Given that many typical workloads on DSP have highly regular data access patterns, this thesis presents a custom Address Generation Unit (AGU) tailored for a proprietary DSP developed by Silicon Integrated to address this challenge.
 The proposed AGU accelerates execution by entirely offloading complex address calculations from the main datapath. It introduces advanced addressing capabilities, including post-modification, modulo, bit-reversal, and multi-dimensional addressing. To strike an optimal balance between physical area overhead and operational flexibility, the first three addressing modes share unified hardware modules, while matrix calculation utilizes an independent dedicated module. Furthermore, the system's memory architecture and Instruction Set Architectures (ISA) is correspondingly refactored to support seamless integration.
 The architectural performance was evaluated using four typical DSP benchmarks: FFT, FIR, IIR, and Matrix Multiplication. The integration of the AGU achieved at least a 50% reduction in execution clock cycles across all workloads, accompanied by substantial code size compression ranging from 10.5% to 46.2%. The physical hardware overhead was evaluated via pre-layout logic synthesis using the TowerJazz 65nm technology node. Although the improved architecture incurs a modest area increase of approximately 10.3% and a total power increase of 16.0%, the drastic reduction in execution time results in a significant decrease in the overall energy consumption per task. Ultimately, this work demonstrates a highly successful architectural enhancement, proving that the proposed AGU delivers a highly favorable energy-efficient DSP acceleration.}},
  author       = {{Kong, Xiaoling}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Address Generation Unit (AGU) for a Custom DSP Core}},
  year         = {{2026}},
}