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Efficient Pre-Silicon Compiler Validation

Farkas, Tristan LU and Bjursten, Olivia LU (2026) EDAN70 20251
Department of Computer Science
Abstract (Swedish)
To validate processor instructions before manufacturing hardware is both a time consuming and costly process. The possibilities now are either depending on slow emulations or developed hardware, which is limiting and ineffective for small architectural changes. In this paper, a new hybrid method for pre-silicon compiler validation is investigated. The normal execution happens on already existing hardware, and new or not yet implemented instructions are handled through external emulation. The method is implemented by letting a separate program trace and detect invalid instructions, emulate their behavior and then continue the program. The technique is benchmarked on an IBM POWER-8 machine by measuring the cost of performance for handling... (More)
To validate processor instructions before manufacturing hardware is both a time consuming and costly process. The possibilities now are either depending on slow emulations or developed hardware, which is limiting and ineffective for small architectural changes. In this paper, a new hybrid method for pre-silicon compiler validation is investigated. The normal execution happens on already existing hardware, and new or not yet implemented instructions are handled through external emulation. The method is implemented by letting a separate program trace and detect invalid instructions, emulate their behavior and then continue the program. The technique is benchmarked on an IBM POWER-8 machine by measuring the cost of performance for handling the invalid instructions by this approach. The results show that handling a single invalid instruction introduces a stable overhead with a median impact of approximately 50 858 clock cycles, but the overall impact varies across programs. The study shows that this method can enable a faster and more flexible validation of architectural changes by combining hardware performance with the emulator flexibility. (Less)
Please use this url to cite or link to this publication:
author
Farkas, Tristan LU and Bjursten, Olivia LU
supervisor
organization
course
EDAN70 20251
year
type
L3 - Miscellaneous, Projetcs etc.
subject
language
English
id
9251640
date added to LUP
2026-09-23 10:53:19
date last changed
2026-09-23 10:53:19
@misc{9251640,
  abstract     = {{To validate processor instructions before manufacturing hardware is both a time consuming and costly process. The possibilities now are either depending on slow emulations or developed hardware, which is limiting and ineffective for small architectural changes. In this paper, a new hybrid method for pre-silicon compiler validation is investigated. The normal execution happens on already existing hardware, and new or not yet implemented instructions are handled through external emulation. The method is implemented by letting a separate program trace and detect invalid instructions, emulate their behavior and then continue the program. The technique is benchmarked on an IBM POWER-8 machine by measuring the cost of performance for handling the invalid instructions by this approach. The results show that handling a single invalid instruction introduces a stable overhead with a median impact of approximately 50 858 clock cycles, but the overall impact varies across programs. The study shows that this method can enable a faster and more flexible validation of architectural changes by combining hardware performance with the emulator flexibility.}},
  author       = {{Farkas, Tristan and Bjursten, Olivia}},
  language     = {{eng}},
  note         = {{Student Paper}},
  title        = {{Efficient Pre-Silicon Compiler Validation}},
  year         = {{2026}},
}