Design and Verification of a Topology-Parametric Network-on-Chip with AXI4-Lite Interface Integration

Abstract

The increasing number of processing elements, memories, and accelerators in modern systems-on-chip places growing demands on on-chip communication. This
thesis presents ToPoNoC, a topology-parametric Network-on-Chip implemented
in Chisel with Mesh, Ring, and hybrid Mesh–Ring configurations. The design
combines packet/flit transport, virtual-channel buffering, deterministic routing,
packet-level arbitration intended to operate round-robin, ready-valid flow control,
and AXI4-Lite endpoint integration through master- and slave-side bridges.
A layered verification methodology is developed to evaluate both the NoC core
and the complete AXI4-Lite bridge–NoC–bridge path. The NoC-core layer focuses
on routing, packet integrity, virtual channels, contention, and backpressure, while
the AXI4-Lite layer checks end-to-end read and write behavior. Transaction-level
monitors and scoreboards are complemented by functional coverage, targeted assertions, regression testing, and retained simulation evidence. For the evaluated
2×2 SimpleMeshNoCWrapper, the final regression completed 14/14 runs, matched
all 1,484 expected packets, reported no verification errors, and reached 100% functional coverage. After reviewed topology-specific structural waivers, statement
and branch coverage reached 99.52% and 88.05%, respectively, satisfying the documented sign-off criteria for this configuration. The hybrid 2×2 Mesh × 2-Ring
AXI4-Lite regression completed 11/11 runs and matched 522/522 expected completions. A 24-run single-source Mesh load sweep measured approximately six
cycles from accepted ingress packet to delivered packet and an observed throughput plateau of approximately one packet every three cycles. A further 24-run
EP0/EP1-to-EP3 contention sweep measured the same aggregate plateau while
maintaining a Jain fairness index of at least 0.9958 across the evaluated loads. At
an aggregate target load of 0.60, the two sources delivered approximately 0.1667
and 0.1668 packets per cycle, respectively. Follow-up source-pair and permanentlybacklogged experiments showed balanced service for all three evaluated source
pairs, with Jain fairness rounding to 1.0000. The reported conclusions remain
limited to the simulated configurations and test scenarios and are not generalized
to all parameter combinations or to physical implementation metrics.

Popular Abstract

Modern chips contain many processors, memories, and specialized computing units that must exchange data quickly and reliably. As systems grow,
shared communication resources can become bottlenecks. A Network-onChip (NoC) addresses this by using routers inside the chip to move data
between components while handling congestion and competing traffic.
This thesis presents ToPoNoC, a configurable NoC implemented in Chisel.
It supports Mesh, Ring, and combined Mesh–Ring structures. The design
also includes AXI4-Lite bridges, allowing standard read and write operations
to be transported through the network.
The design was evaluated using automated verification environments that
checked routing, data integrity, backpressure, contention, and end-to-end
AXI4-Lite communication. For the tested 2×2 Simple Mesh, all 14 regression
runs passed and 1,484 packets were matched correctly. For the tested 2 × 2
Mesh × 2-Ring AXI4-Lite configuration, all 11 regression runs passed and
522 expected transactions matched the observed results.
Performance testing of the 2 × 2 Simple Mesh showed a sustainable rate
of about one packet every three clock cycles on the evaluated path. Under
two-source contention, the round-robin arbitration distributed service almost
equally between the competing sources, while congestion increased delay and
source-side backlog.
The study shows that on-chip communication systems must be evaluated
for both functional correctness and behavior under load.

• author: Luan, Pengxin
• supervisor: Baktash Behmanesh
• organization: Department of Electrical and Information Technology
• course: EITM02 20261
• year: 2026
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Network-on-Chip, Chisel, AXI4-Lite, virtual channel, UVM, functional verification, performance evaluation.
• report number: LU/LTH-EIT 2026-1195
• language: English
• id: 9251809
• date added to LUP: 2026-09-25 10:03:36
• date last changed: 2026-09-25 10:03:36