Ring amplifiers for high speed pipeline assisted SAR ADCs

Abstract

This thesis contains a review of published ring amplifier topologies. It is suggested to split the input stage of the ring amplifier into two. In this way, a robust ring amplifier can be designed without stacking the transistors in the second stage of the ring amplifier, boosting its speed properties. The split input stage can also be used to design a fully differential bias enhanced ring amplifier, boosting the ring amplifiers settling properties at the cost of lower gain. A figure of merit for the ring amplifiers is suggested. The advantages and disadvantages of using ring amplifiers in pipeline assisted SAR ADC is discussed with regards to noise power, linearity, settling speed and PVT robustness. A figure of merit for ring amplifiers is suggested.

A ring amplifier based pipeline assisted SAR ADC is implemented with some non-critical components realized using behavioral modelling. The implemented ADC reaches, SNR 58 dB, SFDR 71 dB, consuming 3.3 mW operating at 550 MHz. The performance of the pipelined SAR ADC is compared with an existing conventional SAR ADC. It is concluded that the ring amplifier is well suited for high speed pipeline assisted SAR ADCs from a noise, linearity and power perspective but it is somewhat limited by its relatively low settling speed.

Popular Abstract

Popular scientific summary: Ring amplifiers for high speed pipeline assisted SAR ADCs
During the two last decades the digital infrastructure has expanded enormously. This has been enabled by the very fast development of transistor technology, where the size of the transistors has decreased exponentially. Often summarized as Moore’s law. This has led to new possibilities of processing data in the digital domain, but also lead to increased strain on the interfaces between the digital and analog world. One of these interfaces is the Analog to digital converters (ADC).
Digital circuits almost always benefit from smaller transistors. For analog circuits is not so simple, some analog circuit does even deteriorate when the transistor becomes increasingly smaller. This has led to a push, where it is attempted to design analog circuits and architectures with as many digital components as possibly.
One such architecture is the successive approximation ADC (SAR ADC). The SAR ADC preforms binary search on the input voltage.
While the SAR ADC is very friendly to small transistors and have low power consumption. The SAR ADC is characterized by low conversion speed and is somewhat limited by noise, injected by the transistors preforming the conversion.
One way of approach this is to split the SAR ADC into the pipeline SAR ADC, figure (b) below. This does however require a residue amplifier, stuffed in between the two ADC in figure (b). Unfortunately, the traditionally used residue amplifier consumes a large part of the total power consumption of the whole ADC.
This have sparked a search for novel residue amplifier that are friendly to small transistors. The thesis is concerned with studying one such amplifier namely the ring amplifier. Ring amplifier is built with inverters, one of the most important design blocks in digital designs. The thesis concludes that ring amplifier have high potential for high speed pipeline SAR ADC. In terms of linearity noise and power consumption but are somewhat limited by low settling speed.

• author: Holmstedt, Johan
• supervisor: Henrik Sjöland
• organization: Department of Electrical and Information Technology
• course: EITM01 20192
• year: 2020
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: ADC SAR RAMP ring amp residue amplifier PVT
• report number: LU/LTH-EIT 2020-746
• language: English
• id: 9006712
• date added to LUP: 2020-03-17 16:24:52
• date last changed: 2020-03-17 16:24:52