Temperature Dependent Electrical Characterisation of Vertical InAs-InGaAs Nanowire MOSFETs

Abstract

This thesis presents the temperature dependence of InGaAs Nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) grown at two different temperatures. The two different growths represent one sample having nanowires which have a mixed crystal structure (showing stacking faults) and one sample with nanowires of pure crystal structure (without stacking faults). The sample with a pure crystal structure was grown at a higher temperature. Both Direct current (DC) and Low-frequency (LF) noise measurements were made on the best devices on the two samples. The DC measurements were made at temperatures ranging from a room temperature of 293 K to a cryogenic temperature of 14 K. The DC characteristics at room temperature show maximum transconductance of and a SS of for the sample with stacking faults and and for the sample without. At 14 K the SS went down to and correspondingly. The LF noise characterization was made at room temperature as well as at a cryogenic temperature of 14 K. The dominant noise source for both samples at room temperature is number fluctuations. The minimum trap density at 10 Hz for the sample with stacking faults was and for the sample without. Measurements made at the cryogenic temperature showed implications of mobility fluctuations being the dominant noise source instead of number fluctuations. The Hooge parameter for the sample with stacking faults was independent of current and was calculated to. For the sample without stacking faults the Hooge parameter varied with the current and was calculated between and. This study does not give any implication that a mix in the crystal structure in InGaAs NW gives any down-grade in performance in terms of subthreshold swing and LF noise.

Popular Abstract

The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is the key to making all computations in electrical circuits possible. They are included in all of our day to day electronic devices and that is what has driven the development of them the last decades. There are also new kinds of applications which increase the demand for improved transistor performance. Quantum computing is an evolving technology which puts a demand for specialized hardware. For the concept to work some parts of the electronic devices need to be able to operate at cryogenic temperatures, temperatures near the absolute zero. At these low temperatures some of the physical behavior of the transistor changes, resulting in new possibilities as well as challenges. The main goal for transistor development has been to shrink their dimensions in order to make them faster and more power efficient. Scaling of transistor dimensions also increases the density or transistor count in an electronic device. The highest transistor count today in 2022 is Apple’s microprocessor M1 Ultra which has 114 billion MOSFETs. However as the size of the transistor decreases, so called short channel effects start to kick in. These short channel effects lead to a number of degradations, like increased power consumption or the gate having less control over the channel. Further traditional scaling is thus counter productive. Nowadays there is ongoing research on how to combat these problems by changing the physical form of the transistors, trying out different materials as well as different ways of production. The nanowire technology together with a III-V semiconductor material is a very promising candidate for future MOSFETs. The nanowire uses the concept of a Gate-All-Around (GAA) which increases the number of dimensions for which the gate has control over the channel. The III-V materials have excellent transport properties which both increase switching speed and decrease power consumption. The combination of the new technology and materials would then counter some of the short channel effects due to over-scaling. This thesis has examined and compared two samples of Vertical InAs-InGaAs Nanowire MOSFETs. The two samples were similar in design but were grown at different temperatures. One of the samples had stacking faults in the nanowires while the other sample, which was grown at a higher temperature, did not have any stacking faults. DC-measurements as well as low frequency noise measurements were done at temperatures ranging from room temperature down to 14 Kelvin, in order to determine if the stacking faults had a negative impact on the performance as well as characterizing the oxide quality of the transistor. The results did not show that reducing stacking faults increased the performance.

• author: Johannesson, Sofie and Skog, Sebastian
• supervisor: Johannes Svensson
• organization: Department of Electrical and Information Technology
• course: EITM01 20221
• year: 2022
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• keywords: Vertical InGaAs Nanowire MOSFET Temperature Dependence Noise
• report number: LU/LTH-EIT 2022-896
• language: English
• id: 9100982
• date added to LUP: 2022-10-31 14:33:57
• date last changed: 2022-10-31 14:33:57