Evaluating the Effects of Microvia Vertical Geometry and Staggering on Signal Integrity

Abstract

Microvias are key enablers of next-generation high-speed and high-density
electronic products. However, their signal-integrity performance can be affected by
manufacturing-induced non-idealities, including tapered sidewalls caused by laser
drilling and positional staggering caused by fabrication tolerances. This thesis
investigates the impact of microvia vertical geometry and manufacturing-induced
staggering on interconnects performance in multilayer Printed Circuit Board
(PCB) structures.
Full-wave electromagnetic simulations are performed to compare conventional
polygonal cylindrical microvia models with more realistic conical microvia
models. For different transition lengths, the antipad size is first optimized
in the cylindrical model to define a matched baseline design. The cylindrical
and conical geometries are then compared using mixed-mode S-parameters,
Time-Domain Reflectometry (TDR), Maximum Available Transmission (MAT),
impedance, and isolation. In addition, manufacturing-induced microvia staggering
is investigated by considering both hole misalignment and layer misalignment.
Representative special cases are used to examine the effects of offset direction
for hole misalignment, and the combined effects of offset direction and fan-out
direction for layer misalignment. Monte Carlo simulations are then performed with
Gaussian-distributed misalignment offsets to evaluate the statistical robustness of
the transition.
The results show that longer and higher-frequency transitions are more
sensitive to the microvia vertical geometry. The conical model leads to noticeable
differences in return loss, mode conversion, TDR, impedance, and isolation
prediction. For manufacturing-induced staggering, the differential-mode reflection
and transmission remain relatively stable in both the representative special
cases and the Monte Carlo simulations, whereas the differential-to-common-mode
conversion is more sensitive to geometrical asymmetry and exhibits a wider
statistical spread under Gaussian-distributed misalignment offsets.
Overall, this work provides useful guidance for microvia modeling,
manufacturing-tolerance evaluation, and robust Signal Integrity (SI) design in
high-speed High-Density Interconnect (HDI) PCB applications.
Keywords: Stacked microvia, differential interconnects, vertical microvia
geometry, conical microvia, staggering, hole misalignment, layer misalignment,
Monte Carlo analysis, SI.

Popular Abstract

Modern electronic products, such as computers, mobile phones, 5G devices, and AI
hardware, are becoming smaller, faster, and more powerful. To make this possible,
printed circuit boards need to contain many dense and high-speed electrical
connections. One important structure used for this purpose is the microvia, which
is a very small hole that connects different layers inside a circuit board.
Although microvias are very small, their shape and position can strongly affect
how well high-speed signals travel through the board. In real manufacturing,
microvias are not always perfectly shaped or perfectly aligned. For example, a
microvia may have a tapered shape due to laser drilling, or its position may be
slightly shifted because of manufacturing tolerances. These small imperfections
can cause signal reflection, signal loss, and unwanted conversion of the useful
signal into noise-like components.
This thesis studies how these manufacturing-related imperfections influence
signal quality in high-speed interconnects. Computer simulations are used to
compare ideal cylindrical microvias with more realistic conical microvias. The
thesis also investigates two types of misalignment: hole misalignment, where the
microvia position shifts, and layer misalignment, where an entire circuit-board
layer is slightly displaced.
The results show that simplified microvia models can be acceptable for
short connections, but more realistic models become important for long and
high-frequency connections. The study also shows that some signal-quality
measures remain relatively stable under small manufacturing errors, while mode
conversion is more sensitive to geometrical asymmetry. These findings can
help engineers build more accurate simulation models and design more reliable
high-speed circuit boards.

• author: Wang, Yimin
• supervisor: Daniel Sjöberg
• organization: Department of Electrical and Information Technology
• course: EITM02 20261
• year: 2026
• type: H2 - Master's Degree (Two Years)
• subject: Technology and Engineering
• report number: LU/LTH-EIT 2026-1164
• language: English
• id: 9238989
• date added to LUP: 2026-06-17 13:52:09
• date last changed: 2026-06-17 13:52:09